Nonvolatile flip-flop using pseudo-spin-transistor architecture and its power-gating applications
Nonvolatile flip-flop using pseudo-spin-transistor architecture and its power-gating applications
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DOI：
10.1109/iscdg.2012.6360000
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发表时间：
2012-11
期刊：
影响因子：
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通讯作者：
S. Yamamoto;Y. Shuto;S. Sugahara
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文献类型：
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作者：
S. Yamamoto;Y. Shuto;S. Sugahara
对一种基于自旋转移矩磁隧道结（STT-MTJ）的伪自旋晶体管结构的新型非易失性延迟触发器（NV-DFF）的性能和功率门控（PG）能力进行了计算分析。NV-DFF的高性能节能PG操作可以通过其采用伪自旋MOSFET（PS-MOSFET）的单元结构来实现，该单元结构可以将STT-MTJ与NV-DFF的普通DFF部分电分离。这种分离还使得NV-DFF的盈亏平衡时间（BET）可以通过PS-MOSFET的尺寸来设计，而不会降低正常DFF操作的性能。分析了NV-DFF与CMOS逻辑系统面积比对BET的影响。尽管优化的最低BET根据面积占用率而变化，但显示实现了具有几个亚微秒BET的节能细粒度PG。我们还提出了使用非易失性分层存储器系统的微处理器和片上系统（SoC），该系统配置有NV-DFF和非易失性静态随机存取存储器（NV-SRAM）。
We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-transistor architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved by its cell structure employing pseudo-spin-MOSFETs (PS-MOSFETs) that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized lowest BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and systems-on-chip (SoCs) using nonvolatile hierarchical-memory systems that are configured with NV-DFFs and nonvolatile static random access memories (NV-SRAMs).