A Pixel-parallel Image Processor Using Logic Pitch-matched To Dynamic Memory
A Pixel-parallel Image Processor Using Logic Pitch-matched To Dynamic Memory
复制标题
一种采用逻辑节距匹配动态存储器的像素并行图像处理器
DOI：
10.1109/4.766817
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发表时间：
1997
期刊：
影响因子：
--
通讯作者：
C. Sodini
中科院分区：
文献类型：
--
作者：
J. Gealow;C. Sodini
像素并行图像处理器为桌面系统提供了实时执行低级别图像处理任务的能力。紧凑的逻辑单元与DRAM列间距匹配，以形成密集的处理元件块。处理元件互连以形成/SPL次/阵列，每个处理元件被分配给单个像素。在一个完整的系统中，以60 ns的时钟周期运行，全功能器件的功耗为300 mW。使用这些设备，已实时执行低级别图像处理任务，并以超过30帧的速率提供输入图像/S。
A pixel-parallel image processor provides the capability for desktop systems to perform low-level image processing tasks in real time. Compact logic units are pitch-matched to DRAM columns to form dense blocks of processing elements. The processing elements are interconnected to form a 64/spl times/64 array, with each processing element assigned to a single pixel. Operating with a 60-ns clock cycle in a complete system, fully functional devices dissipate 300 mW. Using the devices, low-level image processing tasks have been performed in real time with input images provided at rates exceeding 30 frames/s.