On Low Complexity Bit Parallel Polynomial Basis Multipliers
On Low Complexity Bit Parallel Polynomial Basis Multipliers
复制标题
低复杂度位并行多项式基乘法器
DOI：
10.1007/978-3-540-45238-6_16
复制
发表时间：
2003
期刊：
影响因子：
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通讯作者：
M. A. Hasan
中科院分区：
文献类型：
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作者：
A. Reyhani;M. A. Hasan
表示有限域元素的多项式（或标准）的基础上，我们考虑了位并行乘法器架构有限域GF（2m）。这种乘法器的时间和空间复杂度很大程度上取决于定义不可约多项式的域。基于几类重要的不可约多项式，我们给出了乘法器门数和时间延迟的精确复杂性分析。在一般情况下，我们的结果匹配或优于以前已知的最好的结果在类似的类。我们还提出了确切的配方的乘数输出的坐标。这样的公式预计是有用的，有效地实现乘法器使用硬件描述语言，如VHDL和Verilog，而不具有有限域算术的知识。
Representing finite field elements with respect to the polynomial (or standard) basis, we consider a bit parallel multiplier architecture for the finite fieldGF(2m) . Time and space complexities of such a multiplier heavily depend on the field defining irreducible polynomials. Based on a number of important classes of irreducible polynomials, we give exact complexity analyses of the multiplier gate count and time delay. In general, our results match or outperform the previously known best results in similar classes. We also present exact formulations for the coordinates of the multiplier output. Such formulations are expected to be useful to efficiently implement the multiplier using hardware description languages, such as VHDL and Verilog, without having much knowledge of finite field arithmetic.