Optimization of power and energy in FinFET based SRAM cell using adiabatic logic
Optimization of power and energy in FinFET based SRAM cell using adiabatic logic
复制标题
使用绝热逻辑优化基于 FinFET 的 SRAM 单元的功率和能量
DOI：
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
V. S. K. Bhaaskaran
中科院分区：
文献类型：
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作者：
S. Patil;V. S. K. Bhaaskaran
背景/目的：近年来，电路的瞬时功耗和总能量耗散已成为复杂VLSI系统设计方案中需要考虑的重要因素。绝热逻辑是一种优化电路功耗和能量恢复能力的技术，它使VLSI电路能够重复利用消耗的功耗。本文比较了文献中提出的不同绝热SRAM单元结构。此外，传统的SRAM单元和所有相关的设计都是使用针对低功率操作能力的FinFET器件来实现的。方法/统计分析：SRAM单元设计在Cadence® EDA环境中进行，并针对CMOS工艺（即180 nm和32 nm以及随后的32 nm FinFET技术）估计功率和能量值。这两种不同的技术库已被用来确定较低的技术节点效应对功耗的影响。这些SRAM单元的布局是使用Cadence® Asynchronous工具绘制的。调查结果：结果表明，基于FinFET的绝热SRAM单元（8 T和9 T单元结构）的功耗低于传统的基于6 T CMOS的SRAM单元。结论/改进：本文比较了传统SRAM单元和不同工艺节点的绝热SRAM单元，即DSM和UDSM的功耗和能量值。与传统的6 T CMOS SRAM单元相比，绝热逻辑显示出更低的功率和能量消耗。此外，基于FinFET器件的电路描绘了其对器件沟道的更好控制和减少的短沟道效应的优点，从而导致减少的泄漏功率。基于FinFET的SRAM单元采用绝热逻辑，导致最小的功耗和能量耗散。
Background/Objective: In the recent years, the instantaneous power consumption and the total energy dissipation of a circuit have become very important factors to be considered in complex VLSI system design solutions. The adiabatic logic is a technique, which is used to optimize the power dissipation and the energy recovery capability of these circuits, and this logic makes the VLSI circuits reuse the consumed power. This paper compares different adiabatic SRAM cell structures presented in the literature. Furthermore, the conventional SRAM cell and all the related designs are implemented using FinFET devices aiming at low power operation capability. Methods/Statistical analysis: The SRAM cell design is carried out in Cadence® EDA environment and power and energy values are estimated for the CMOS processes, namely, 180nm and 32nm followed by the 32nm FinFET technology. The two different technology libraries have been employed to identify the effects of the lower technology nodal effect on the power dissipation. The layouts for these SRAM cells have been drawn using Cadence® Assura tool. Findings: The results show that the power consumption of the FinFET based adiabatic SRAM cells (8T and 9T cell structure) is less than the conventional 6T CMOS based SRAM cell. Conclusion/improvement: In this paper, the conventional SRAM cell and the adiabatic SRAM cells with different technology nodes, namely, DSM and UDSM are compared for their power and energy values. The adiabatic logic displays lower power and energy consumption compared to those incurred by the conventional 6T CMOS SRAM cell. Furthermore, the FinFET device based circuits portrays advantages with its better control over the device channel and reduced short channel effects, resulting in reduced leakage power. The FinFET based SRAM cell employing the adiabatic logic incurs the minimum power and energy dissipation.