Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs
Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs
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DOI：
10.1109/fpl60245.2023.00010
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发表时间：
2023-08
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影响因子：
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通讯作者：
Gabriel Rodriguez-Canal;Nick Brown;Timothy Dykes;Jessica R. Jones;U. Haus
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作者：
Gabriel Rodriguez-Canal;Nick Brown;Timothy Dykes;Jessica R. Jones;U. Haus
近年来，使用现场可编程门阵列（FPGA）来加速科学应用的情况有所增加，众多应用展示了FPGA在高性能工作负载方面的优势。然而，虽然高层次综合（HLS）通过使程序员能够使用C++显著降低了FPGA编程的入门门槛，但一个主要挑战是，这些代码大多数情况下最初并不是用C++编写的。相反，Fortran是科学计算的通用语言，因此，甚至在考虑FPGA之前，就需要一个复杂且耗时的初始步骤将其转换为C++。在本文中，我们描述了通过将LLVM Flang前端连接到AMD Xilinx的LLVM后端，使Fortran能够用于AMD Xilinx FPGA的工作。这使程序员能够将Fortran作为FPGA编程的一流语言，并且正如我们所展示的，能够享受HLS C++所提供的所有调优和优化机会。此外，我们证明了Fortran的某些语言特性使其相较于C++在FPGA编程方面尤其具有优势。这项工作的结果是降低了在科学计算中使用FPGA的入门门槛，使程序员能够直接在FPGA上利用他们现有的代码库和所选语言。
In recent years the use of FPGAs to accelerate scientific applications has grown, with numerous applications demonstrating the benefit of FPGAs for high performance workloads. However, whilst High Level Synthesis (HLS) has significantly lowered the barrier to entry in programming FPGAs by enabling programmers to use C++, a major challenge is that most often these codes are not originally written in C++. Instead, Fortran is the lingua franca of scientific computing and-so it requires a complex and time consuming initial step to convert into C++ even before considering the FPGA. In this paper we describe work enabling Fortran for AMD Xilinx FPGAs by connecting the LLVM Flang front end to AMD Xilinx's LLVM back end. This enables programmers to use Fortran as a first-class language for programming FPGAs, and as we demonstrate enjoy all the tuning and optimisation opportunities that HLS C++ provides. Furthermore, we demonstrate that certain language features of Fortran make it especially beneficial for programming FPGAs compared to C++. The result of this work is a lowering of the barrier to entry in using FPGAs for scientific computing, enabling programmers to leverage their existing codebase and language of choice on the FPGA directly.