Flexible Parallel Architecture for DVB-S2 LDPC Decoders
Flexible Parallel Architecture for DVB-S2 LDPC Decoders
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DOI：
10.1109/glocom.2007.619
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发表时间：
2007-12
期刊：
影响因子：
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通讯作者：
M. Gomes;G. F. P. Fernandes;V. Silva;V. Ferreira;A. Sengo;M. Falcão
中科院分区：
文献类型：
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作者：
M. Gomes;G. F. P. Fernandes;V. Silva;V. Ferreira;A. Sengo;M. Falcão
DVB-S2标准采用的最先进的低密度奇偶校验(LDPQ)码的解码器，探索选定的特殊LDPC-IRA码的周期性M=360特征。本文对一种著名的M-核并行硬件结构进行了推广，提出了一种在不增加内存寻址开销的情况下，保持消息映射机制不变的任意M因子的有效划分方法。该方法为降低译码复杂度提供了一种简单有效的途径。使用Xilinx公司的FPGA系列对所提出的针对N={45，90,180}个并行处理单元的解码器架构进行了综合，结果显示最小吞吐量超过最小90 Mbps。
State-of-the-art decoders for Low-Density Parity-Check (LDPQ codes adopted by the DVB-S2 standard, explore the periodicity M = 360 features of the selected special LDPC- IRA codes. This paper addresses the generalization of a well known M-kernel parallel hardware structure and proposes an efficient partitioning by any factor of M, without memory addressing overhead and keeping unchanged the efficient message mapping scheme. The method provides a simple and efficient way to reduce the decoder complexity. Synthesizing the proposed decoder architecture for N = {45,90,180} parallel processing units using an FPGA family from Xilinx shows a minimum throughput above the minimal 90 Mbps.