A high speed open source controller for FPGA Partial Reconfiguration
A high speed open source controller for FPGA Partial Reconfiguration
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DOI：
10.1109/fpt.2012.6412113
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发表时间：
2012-12
期刊：
影响因子：
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通讯作者：
Kizheppatt Vipin;Suhaib A. Fahmy
中科院分区：
文献类型：
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作者：
Kizheppatt Vipin;Suhaib A. Fahmy
部分重配置 (PR) 是一项先进技术，通过覆盖部分配置存储器，允许在运行时重新配置部分设计，从而提高 FPGA 的灵活性。 PR 是实施自适应系统的重要推动者。然而，此类系统的设计可能具有挑战性，对于配置控制器来说尤其如此。通常支持的方法和 IP 吞吐量较低，导致配置时间较长，从而无法在需要快速操作的系统中进行 PR。在本文中，我们提出了一种高速配置控制器，它提供了多种在自适应系统中有用的功能。该设计已发布，供更广泛的研究界使用。
Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. PR is an important enabler for implementing adaptive systems. However, the design of such systems can be challenging, and this is especially true of the configuration controller. The generally supported methods and IP have low throughput, resulting in long configuration time that precludes PR from systems where this operation needs to be fast. In this paper, we present a high-speed configuration controller that provides several features useful in adaptive systems. The design has been released for use by the wider research community.