High-performance and low-power challenges for sub-70 nm microprocessor circuits
High-performance and low-power challenges for sub-70 nm microprocessor circuits
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DOI：
10.1109/cicc.2002.1012781
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发表时间：
2002-08
期刊：
影响因子：
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通讯作者：
R. Krishnamurthy;A. Alvandpour;V. De;S. Borkar
中科院分区：
文献类型：
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作者：
R. Krishnamurthy;A. Alvandpour;V. De;S. Borkar
CMOS技术在70 nm节点以上的扩展变得越来越困难，为高性能和低功耗微处理器提出了新的设计挑战。本文讨论了所需的一些关键范式转变。本发明描述用以对抗（i）增加的切换及泄漏功率耗散、（ii）大信号高速缓冲存储器阵列及寄存器堆的不良泄漏容限及（iii）恶化的全球芯片上互连缩放趋势的电路技术。
CMOS technology scaling is becoming difficult beyond 70 nm node, raising new design challenges for high-performance and low-power microprocessors. This paper discusses some of the key paradigm shifts required. Circuit techniques to combat (i) increasing switching and leakage power dissipation, (ii) poor leakage tolerance of large-signal cache arrays and register files, and (iii) worsening global on-chip interconnect scaling trend, are described.