Thin hybrid pixel assembly with backside compensation layer on ROIC
Thin hybrid pixel assembly with backside compensation layer on ROIC
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DOI：
10.1088/1748-0221/12/01/c01018
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发表时间：
2017-01
影响因子：
1.3
通讯作者：
R. Bates;C. Buttar;T. Mcmullen;L. Cunningham;J. Ashby;F. Doherty;C. Gray;G. Pares;L. Vignoud-L.-V
中科院分区：
文献类型：
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作者：
R. Bates;C. Buttar;T. Mcmullen;L. Cunningham;J. Ashby;F. Doherty;C. Gray;G. Pares;L. Vignoud-L.-V
整个ATLAS内部跟踪系统将在HL-LHC的运行中被替换。这将包括一个明显更大的像素探测器，约15平方米。对于这个项目，减少混合像素模块的质量至关重要，这需要将传感器和读出芯片都减薄到大约150微米。硅芯片的减薄导致SnAg凸块的低凸块产量，这是由于在焊料回流阶段两个芯片的不良共面性在像素阵列内产生死区。在ATLAS FEI 4像素读出芯片减薄到100微米的情况下，芯片是凹形的，正面受压，在室温下弯曲+100微米，在SnAg焊料回流温度下弯曲-175微米，这是由CMOS堆叠和硅衬底中的材料之间的CTE失配引起的。为了解决凸块成品率低的问题，提出了一种新的圆片级工艺，即通过控制芯片弯曲度来实现凸块成品率的控制。SiN和Al：Si的背侧电介质和金属叠层已经沉积在读出芯片晶片上以动态地补偿前侧叠层的应力。为了与3D工艺保持一致，所使用的材料与硅通孔（TSV）技术兼容，该技术采用TSV最后方法，该方法正在开发中。结果表明，可以通过SiN/Al：Si叠层的沉积条件和厚度来操纵校正的幅度。迄今为止最好的样品在温度范围内的弯曲幅度几乎减少了4倍，弯曲的符号（模具的形状）保持不变。背侧沉积条件的进一步发展正在进行中，目标是在回流焊温度下接近零弯曲，并且在整个温度范围内弯曲幅度最小。从FEI 4读出晶片减薄到100微米与背面补偿层生产的组件已首次制成，并证明债券收益率接近100%。
The entire ATLAS inner tracking system will be replaced for operation at the HL-LHC . This will include a significantly larger pixel detector of approximately 15 m2. For this project, it is critical to reduce the mass of the hybrid pixel modules and this requires thinning both the sensor and readout chips to about 150 micrometres each. The thinning of the silicon chips leads to low bump yield for SnAg bumps due to bad co-planarity of the two chips at the solder reflow stage creating dead zones within the pixel array. In the case of the ATLAS FEI4 pixel readout chip thinned to 100 micrometres, the chip is concave, with the front side in compression, with a bow of +100 micrometres at room temperature which varies to a bow of −175 micrometres at the SnAg solder reflow temperature, caused by the CTE mismatch between the materials in the CMOS stack and the silicon substrate. A new wafer level process to address the issue of low bump yield be controlling the chip bow has been developed. A back-side dielectric and metal stack of SiN and Al:Si has been deposited on the readout chip wafer to dynamically compensate the stress of the front side stack. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach which is under development for this chip. It is demonstrated that the amplitude of the correction can be manipulated by the deposition conditions and thickness of the SiN/Al:Si stack. The bow magnitude over the temperature range for the best sample to date is reduced by almost a factor of 4 and the sign of the bow (shape of the die) remains constant. Further development of the backside deposition conditions is on-going with the target of close to zero bow at the solder reflow temperature and a minimal bow magnitude throughout the temperature range. Assemblies produced from FEI4 readout wafers thinned to 100 micrometres with the backside compensation layer have been made for the first time and demonstrate bond yields close to 100%.