An Efficient VLSI Architecture for Nonbinary LDPC Decoders
An Efficient VLSI Architecture for Nonbinary LDPC Decoders
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DOI：
10.1109/tcsii.2009.2036542
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
Jun Lin;Jin Sha;Zhongfeng Wang;Li Li-Li
中科院分区：
文献类型：
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作者：
Jun Lin;Jin Sha;Zhongfeng Wang;Li Li-Li
在有限域GF（q）上构造的低密度奇偶校验（LDPC）码，又称非二进制LDPC码，是二进制LDPC码的扩展，具有更好的性能。虽然已经提出了各种低复杂度的准最优迭代译码算法，但由于非二进制LDPC译码器的硬件不友好特性，其VLSI实现很少被讨论。本文提出了一种有效的选择性计算算法，它完全避免了排序过程。此外，一个有效的VLSI结构的非二进制Min-Max解码器。综合结果证明了所提出的技术的效率。
Low-density parity-check (LDPC) codes constructed over the Galois field GF(q), which are also called nonbinary LDPC codes, are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity quasi-optimal iterative decoding algorithms have been proposed, the VLSI implementation of nonbinary LDPC decoders has rarely been discussed due to their hardware unfriendly properties. In this brief, an efficient selective computation algorithm, which totally avoids the sorting process, is proposed for Min-Max decoding. In addition, an efficient VLSI architecture for a nonbinary Min-Max decoder is presented. The synthesis results are given to demonstrate the efficiency of the proposed techniques.