Improving fault tolerance utilizing hardware-software-co-synthesis
Improving fault tolerance utilizing hardware-software-co-synthesis
复制标题
利用硬件-软件-协同综合提高容错能力
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
G. Fey
中科院分区：
文献类型：
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作者：
Heinz Riener;Stefan Frehse;G. Fey
嵌入式系统由硬件和软件组成，在安全关键和任务关键领域无处不在。随着现代数字电路集成密度的不断提高，嵌入式系统越来越容易受到瞬态故障的影响。提高容错性的技术通常在硬件或软件中实现。本文从硬件和软件两方面研究了提高嵌入式系统容错能力的综合技术。提出了一种贪婪算法，该算法从一组现有的技术中迭代地评估基于处理器的系统的容错能力，并决定系统中哪些组件需要加固。我们在一个简单的案例研究中使用交通碰撞避免系统（TCAS）来评估该算法。
Embedded systems consist of hardware and software and are ubiquitous in safety-critical and mission-critical fields. The increasing integration density of modern, digital circuits causes an increasing vulnerability of embedded systems to transient faults. Techniques to improve the fault tolerance are often either implemented in hardware or in software. In this paper, we focus on synthesis techniques to improve the fault tolerance of embedded systems considering hardware and software. A greedy algorithm is presented which iteratively assesses the fault tolerance of a processor-based system and decides which components of the system have to be hardened choosing from a set of existing techniques. We evaluate the algorithm in a simple case study using a Traffic Collision Avoidance System (TCAS).