Implementation of Chaotic Encryption Architecture on FPGA for On-Chip Secure Communication*
Implementation of Chaotic Encryption Architecture on FPGA for On-Chip Secure Communication*
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DOI：
10.1109/igessc55810.2022.9955334
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发表时间：
2022-11
期刊：
影响因子：
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通讯作者：
Ravi Monani;Brian Rogers;Amin Rezaei;A. Hedayatipour
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文献类型：
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作者：
Ravi Monani;Brian Rogers;Amin Rezaei;A. Hedayatipour
混沌是非线性系统的一种有趣现象，由于其复杂且不可预测的行为而出现。随着低功耗边缘计算设备的不断使用，边缘数据安全对通信安全提出了需求。两个不同的混沌系统具有各自独特的初始条件，混沌随时间同步的特性，是混沌在通信中实现的基础。本文提出了一种适合片上传感器通信的加密架构，以提供使用不同混沌方程在同一芯片上加密的安全性 POC（概念验证）。在通信中，加密是借助微控制器或软件实现来实现的，这些微控制器或软件实现使用更多功率并且具有复杂的硬件实现。小型物联网设备预计将以低功耗运行并受到尺寸限制。同时，这些设备非常容易受到安全威胁，这提高了对低功耗/尺寸的基于硬件的安全性的需求。自从混沌方程被发现以来，它们已被用于各种加密应用中。这项研究的目标是将混沌实现带到 CMOS 级别，传感器位于同一芯片上。硬件协同仿真在用于 Chua 加密/解密架构的 FPGA 板上进行了演示。 Lorenz、SprottD 和 Chua 在 FPGA 上的硬件利用率是通过 Xilinx System Generation (XSG) 工具箱实现的，这表明 Lorenz 的利用率比 Chua 低约 9%。
Chaos is an interesting phenomenon for nonlinear systems that emerges due to its complex and unpredictable behavior. With the escalated use of low-powered edge-compute devices, data security at the edge develops the need for security in communication. The characteristic that Chaos synchronizes over time for two different chaotic systems with their own unique initial conditions, is the base for chaos implementation in communication. This paper proposes an encryption architecture suitable for communication of on-chip sensors to provide a POC (proof of concept) with security encrypted on the same chip using different chaotic equations. In communication, encryption is achieved with the help of microcontrollers or software implementations that use more power and have complex hardware implementation. The small IoT devices are expected to be operated on low power and constrained with size. At the same time, these devices are highly vulnerable to security threats, which elevates the need to have low power/size hardware-based security. Since the discovery of chaotic equations, they have been used in various encryption applications. The goal of this research is to take the chaotic implementation to the CMOS level with the sensors on the same chip. The hardware co-simulation is demonstrated on an FPGA board for Chua encryption/decryption architecture. The hardware utilization for Lorenz, SprottD, and Chua on FPGA is achieved with Xilinx System Generation (XSG) toolbox which reveals that Lorenz’s utilization is ~9% lesser than Chua’s.