A 64–84-GHz PLL With Low Phase Noise in an 80-GHz SiGe HBT Technology
A 64–84-GHz PLL With Low Phase Noise in an 80-GHz SiGe HBT Technology
复制标题
采用 80-GHz SiGe HBT 技术、具有低相位噪声的 64–84-GHz PLL
DOI：
10.1109/tmtt.2012.2213833
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发表时间：
2012
影响因子：
4.3
通讯作者：
H. Schumacher
中科院分区：
文献类型：
--
作者：
Gang Liu;A. Trasser;H. Schumacher
本文提出了一种低成本的80-GHz HBT技术实现的64-84-GHz锁相环（PLL）。该电路由宽调谐范围压控振荡器、推挽倍频器、32分频器、鉴相器和有源环路滤波器组成。在1 MHz偏移处测得的相位噪声为-106 dBc/Hz。在64 GHz时输出功率为-2.5 dBm，在84 GHz时缓慢下降到-8.1 dBm，最大直流功耗为517 mW。据作者所知，该电路实现了最宽的频率调谐范围，其带内相位噪声是最低的完全集成的V/W波段PLL的报告日期。
This paper presents a 64-84-GHz phase-locked loop (PLL) realized in a low-cost 80-GHz HBT technology. The circuit consists of a wide tuning-range voltage-controlled oscillator, a push-push frequency doubler, a divide-by-32 frequency divider, a phase detector and an active loop filter. The measured phase noise at 1-MHz offset is -106 dBc/Hz. The output power is -2.5 dBm at 64 GHz, and it slowly decreases to -8.1 dBm at 84 GHz, with a maximum dc power consumption of 517 mW. To the authors' knowledge, the circuit achieves the widest frequency tuning range and its in-band phase noise is the lowest among the fully integrated V/W-band PLLs reported to date.