An On-Chip-Trainable Gaussian-Kernel Analog Support Vector Machine
An On-Chip-Trainable Gaussian-Kernel Analog Support Vector Machine
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DOI：
10.1109/tcsi.2009.2034234
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发表时间：
2010-07-01
影响因子：
5.1
通讯作者：
Shibata, Tadashi
中科院分区：
文献类型：
--
作者：
Kang, Kyunghee;Shibata, Tadashi
提出了一种具有片上训练能力的高斯核支持向量机模拟电路结构。它具有可扩展的阵列处理器配置，并且电路大小仅与学习样本的数量成比例地增加。由于本文采用了硬件友好的算法，通过在支持向量机分类硬件上附加一个小的附加电路来实现学习功能。支持向量机分类硬件由一组高斯电路组成。虽然该系统本质上是模拟的，但包括训练结果在内的输入和输出信号都是数字格式的。因此，学习的参数很容易存储和在训练课程后重复使用。采用0.18微米工艺设计并制作了一款包含2级、2维、12模板分类器的概念验证芯片。给出了制作芯片的实验结果，并与理论计算结果进行了比较。该芯片每秒可识别8.7×10(5)个矢量，平均功耗为220微瓦。用8个芯片测试了学习能力，并评估了芯片之间的变异性。测试结果证实了芯片的成功运行，表明片上学习可以补偿模拟的缺陷。
An analog circuit architecture of Gaussian-kernel support vector machines having on-chip training capability has been developed. It has a scalable array processor configuration and the circuit size increases only in proportion to the number of learning samples. Thanks to the hardware-friendly algorithm employed in the present work, the learning function is realized by attaching a small additional circuitry to the SVM classifying hardware. The SVM classifying hardware is composed as an array of Gaussian circuits. Although the system is inherently analog, the input and output signals including training results are all available in digital format. Therefore, the learned parameters are easily stored and reused after training sessions. A proof-of concept chip containing 2-class, 2-D, 12-template classifier was designed and fabricated in a 0.18-mu m CMOS technology. The experimental results obtained from the fabricated chips are presented and compared with theoretical calculation results. It can classify 8.7 x 10(5) vectors per second and the average power dissipation was 220 mu W. The learning capability was tested using eight fabricated chips and the variability among these chips were evaluated. Successful operation of the chips was confirmed by measurement results, which demonstrates that on-chip-learning can compensate for analog imperfections.