Universal transfer of full‐class metal electrodes for barrier‐free two‐dimensional semiconductor contacts

Universal transfer of full‐class metal electrodes for barrier‐free two‐dimensional semiconductor contacts
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DOI:
10.1002/inf2.12491
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发表时间:
2023-11
期刊:
影响因子:
22.7
通讯作者:
Mengyu Hong;Xiankun Zhang;Yu Geng;Yunan Wang;Xiaofu Wei;L. Gao;Huihui Yu;Zhihong Cao;Zheng Zhang;Yue Zhang
Mengyu Hong;Xiankun Zhang;Yu Geng;Yunan Wang;Xiaofu Wei;L. Gao;Huihui Yu;Zhihong Cao;Zheng Zhang;Yue Zhang
中科院分区:
材料科学1区
文献类型:
--
作者:
Mengyu Hong;Xiankun Zhang;Yu Geng;Yunan Wang;Xiaofu Wei;L. Gao;Huihui Yu;Zhihong Cao;Zheng Zhang;Yue Zhang

文献摘要

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金属-半导体接触是半导体器件中的关键部件。超薄二维过渡金属二硫属化物半导体可以支持下一代集成电路的晶体管缩放。然而,它们的性能通常会因传统的金属沉积而降低,这会因化学无序和费米能级钉扎(FLP)而导致高势垒。虽然转移电极可以解决这些问题,但由于预沉积金属和基底之间的强粘附力,它们在实现全类金属的通用转移方面受到限制。在这里,我们提出了一种纳米带辅助转移策略,可以避免粘附限制,并实现20多种不同类型电极的通用转移。我们的接触服从Schottky-Mott规则,并表现出S = 0.99的FLP。电子和空穴接触都显示出创纪录的低肖特基势垒,分别为4.2和11.2 meV。作为演示,我们使用这些高性能触点构建了一个无掺杂的WSe 2逆变器,其静态功耗仅为58 pW。该策略为构建高性能后摩尔电子器件提供了电极制备的通用方法。
Metal–semiconductor contacts are crucial components in semiconductor devices. Ultrathin two‐dimensional transition‐metal dichalcogenide semiconductors can sustain transistor scaling for next‐generation integrated circuits. However, their performance is often degraded by conventional metal deposition, which results in a high barrier due to chemical disorder and Fermi‐level pinning (FLP). Although, transferring electrodes can address these issues, they are limited in achieving universal transfer of full‐class metals due to strong adhesion between pre‐deposited metals and substrates. Here, we propose a nanobelt‐assisted transfer strategy that can avoid the adhesion limitation and enables the universal transfer of over 20 different types of electrodes. Our contacts obey the Schottky–Mott rule and exhibit a FLP of S = 0.99. Both the electron and hole contacts show record‐low Schottky barriers of 4.2 and 11.2 meV, respectively. As a demonstration, we construct a doping‐free WSe2 inverter with these high‐performance contacts, which exhibits a static power consumption of only 58 pW. This strategy provides a universal method of electrode preparation for building high‐performance post‐Moore electronic devices.