Fabrication Process for Low- T c Superconductor Electronics Devices and Its Future Prospects
Fabrication Process for Low- T c Superconductor Electronics Devices and Its Future Prospects
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低温超导电子器件的制备工艺及其未来展望
DOI：
10.2221/jcsj.52.315
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发表时间：
2017
期刊：
影响因子：
--
通讯作者：
S. Nagasawa
中科院分区：
文献类型：
--
作者：
M. Hidaka;S. Nagasawa
简介：我们经常使用三种基于Nb的制造工艺来制造许多超导数字器件。其中一个由9个Nb、1个Mo和1个Nb/AlOx/Nb约瑟夫森结(JJ)层组成。提高了器件参数的可控性，如JJ的临界电流密度(Jc)。对于2016年生产的所有18个晶圆，Nb 9层工艺的Jc被控制在10kA/cm2目标值的±10%以内。对于JJ尺寸为0.5m2的集成电路应用，临界电流的均匀度满足我们的标准。Nb9层工艺的可靠性达到了100,000 JJ电路级别。通过引进先进的制造设备和/或集成新材料，数字电路工艺将得到改进。基于这些数字设备，正在开发三维、模拟、模拟-数字单片和量子计算设备
Synopsis : We are routinely fabricating many superconducting digital devices using three types of Nb-based fabrication process. One of them consists of nine Nb, one Mo and one Nb/AlOx/Nb Josephson junction (JJ) layers. Controllability in the device parameters, such as the critical current density ( J c ) of JJ, has been improved. J c in the Nb 9-layer process was controlled within ±10% of the 10 kA/cm 2 target value for all 18 wafers fabricated in 2016. Uniformity of the critical current satisfied our criteria for integrated circuit applications up to a JJ size of 0.5 m 2 . Reliability of the Nb 9-layer process reached the 100,000 JJ circuit level. The digital circuit processes will be improved by introducing advanced fabrication machines and/or integrating new materials. Three-dimensional, analog, analog-digital monolithic and quantum computing devices are being developed based on these digital device
使用超导铌基电流偏置动感电感探测器进行中子探测
影响因子：
3.6
作者：
Shishido Hiroaki;Yamaguchi Hiroyuki;Miki Yuya;Miyajima Shigeyuki;Oikawa Kenichi;Harada Masahide;Hidaka Mutsuo;Oku Takayuki;Arai Masatoshi;Fujimaki Akira;Ishida Takekazu
通讯作者：
Ishida Takekazu