AFS: Accurate, Fast, and Scalable Error-Decoding for Fault-Tolerant Quantum Computers

AFS: Accurate, Fast, and Scalable Error-Decoding for Fault-Tolerant Quantum Computers
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AFS:用于容错量子计算机的准确、快速且可扩展的错误解码

DOI:
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发表时间:
2022
期刊:
International Symposium on High-Performance Computer Architecture
影响因子:
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通讯作者:
Nicolas Delfosse
Nicolas Delfosse
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--
文献类型:
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作者:
Poulami Das;C. Pattison;Srilatha Manne;Douglas M. Carmean;K. Svore;Moinuddin K. Qureshi;Nicolas Delfosse

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量子计算机有望为各个应用领域的许多重要问题提供计算优势。不幸的是,物理量子设备很容易出现错误,从而限制我们运行大多数量子应用程序。需要量子纠错 (QEC) 代码来实现容错量子计算机 (FTQC),以便在执行计算时不会遇到错误。错误解码是量子纠错的关键组成部分,负责将 QEC 代码生成的一组量子位测量值(称为校正子)转换为错误位置和错误类型。为了实现可行性,错误解码器不仅必须高精度地识别错误,而且还必须快速且可扩展到大量量子位。不幸的是,大多数关于错误解码的先前工作主要只关注准确性,并且依赖于速度太慢而无法实际使用的软件实现。此外,这些研究仅着眼于设计单个解码器,并未分析在具有数千个量子位的大型系统中执行纠错时扩展存储和带宽要求所涉及的挑战。在本文中,我们提出了 AFS,一种准确、快速且可扩展的解码器架构,旨在在具有数百个逻辑量子位的系统环境中运行。我们提出了 AFS 的硬件实现,它基于 Union Find 解码算法并采用三级流水线设计。与最近基于 SFQ 的硬件解码器(逻辑错误率为 6×10−10,物理错误率为 10−3)相比,AFS 提供了高几个数量级的精度和低解码延迟(平均 42 ns),同时对 QEC 周期期间提取综合症时引入的测量误差具有鲁棒性。我们还通过跨多个解码单元共同设计微架构,减少了在所有逻辑量子位上同时执行 QEC 所需的解码硬件数量。我们提出的联合解码器架构 (CDA) 将存储开销减少了 70%(10MB 至 2.8MB)。最后,我们通过利用校正子的稀疏性并压缩数据来减少将校正子从量子位传输到解码器所需的带宽开销。我们提出的综合症压缩将带宽要求平均降低了 30 倍。
Quantum computers promise computational advantages for many important problems across various application domains. Unfortunately, physical quantum devices are highly susceptible to errors that limit us from running most of these quantum applications. Quantum Error Correction (QEC) codes are required to implement Fault-Tolerant Quantum Computers (FTQC) on which computations can be performed without encountering errors. Error decoding is a critical component of quantum error correction and is responsible for transforming a set of qubit measurements generated by the QEC code, called the syndrome, into error locations and error types. For the feasibility of implementation, error decoders must not only identify errors with high accuracy, but also be fast and scalable to a large number of qubits. Unfortunately, most of the prior works on error decoding have focused primarily only on the accuracy and have relied on software implementations that are too slow to be of practical use. Furthermore, these studies only look at designing a single decoder and do not analyze the challenges involved in scaling the storage and bandwidth requirements when performing error correction in large systems with thousands of qubits.In this paper, we present AFS, an accurate, fast, and scalable decoder architecture that is designed to operate in the context of systems with hundreds of logical qubits. We present the hardware implementation of AFS, which is based on the Union Find decoding algorithm and employs a three-stage pipelined design. AFS provides orders of magnitude higher accuracy compared to recent SFQ-based hardware decoders (logical error rate of 6×10−10 for physical error rate of 10−3) and low decoding latency (42ns on average), while being robust to measurement errors introduced while extracting syndromes during the QEC cycles. We also reduce the amount of decoding hardware required to perform QEC simultaneously on all the logical qubits by co-designing the micro-architecture across multiple decoding units. Our proposed Conjoined-Decoder Architecture (CDA) reduces the storage overhead by 70% (10MB to 2.8MB). Finally, we reduce the bandwidth overheads required to transmit syndromes from the qubits to the decoders by exploiting the sparsity in the syndromes and compressing the data. Our proposed Syndrome Compression reduces the bandwidth requirement by 30x, on an average.
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