Degradation of SiC MOSFETs Under High-Bias Switching Events
Degradation of SiC MOSFETs Under High-Bias Switching Events
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DOI：
10.1109/jestpe.2021.3064288
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发表时间：
2022-10-01
影响因子：
5.5
通讯作者：
Zhang, Yuhao
中科院分区：
文献类型：
--
作者：
Kozak, Joseph P.;Zhang, Ruizhe;Zhang, Yuhao
评估功率半导体器件的鲁棒性是将其应用于电力电子应用的关键。最近的静态加速测试表明，SiC金属氧化物半导体场效应晶体管（MOSFET）可以在高于额定电压的阻断电压和雪崩边界附近安全运行数千小时。这项工作评估了SiC MOSFET在连续、硬开关、关断应力下的高偏置鲁棒性，直流偏置高于器件额定电压。在这种高偏置开关条件下，SiC MOSFET在25摄氏度下仅需数十小时，在100摄氏度下只需数十分钟即可出现退化。两个独立的退化和故障机制被揭露：一个存在于栅极氧化物和其他在体半导体区域，其特征在于在栅极漏电流和漏漏电流的增加，分别。第二种退化机制以前没有在文献中报道，它被发现与电子跳跃沿着在开关测试中产生的半导体中的缺陷。与静态加速测试的比较表明，这两个退化机制相关的高偏置开关瞬态，而不是高偏置阻断状态。这些结果表明SiC MOSFET在高偏置、硬开关条件下的鲁棒性不足，以及使用基于开关的测试来评估器件鲁棒性的重要性。
Evaluating the robustness of power semiconductor devices is key for their adoption into power electronics applications. Recent static acceleration tests have revealed that SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) can safely operate for thousands of hours at a blocking voltage higher than the rated voltage and near the avalanche boundary. This work evaluates the high-bias robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc bias higher than the device rated voltage. Under this high-bias switching condition, SiC MOSFETs show degradation in merely tens of hours at 25 degrees C and tens of minutes at 100 degrees C. Two independent degradation and failure mechanisms are unveiled: one present in the gate oxide and the other in the bulk-semiconductor regions, featured by the increase in the gate leakage current and the drain leakage current, respectively. The second degradation mechanism has not been previously reported in the literature; it is found to be related to the electron hopping along with the defects in semiconductors generated in the switching tests. The comparison with the static acceleration tests reveals that both degradation mechanisms correlate to the high-bias switching transients rather than the high-bias blocking states. These results suggest the insufficient robustness of SiC MOSFETs under high-bias, hard-switching conditions and the significance of using switching-based tests to evaluate the device robustness.