A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance
A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance
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DOI：
10.1109/tcad.2010.2042899
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发表时间：
2010-04
影响因子：
2.9
通讯作者：
R. Thakker;C. Sathe;M. Baghini;M. Patil
中科院分区：
文献类型：
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作者：
R. Thakker;C. Sathe;M. Baghini;M. Patil
本文提出了一种新的基于表格的方法，有效的统计分析芬菲尔德效应晶体管电路。所提出的方法使用了一种新的方案，内插的查找表（LUT）的过程参数。各种工艺参数的影响，即，研究了三种电路的沟道长度、鳍片宽度和有效氧化物厚度：缓冲链、静态随机存取存储器单元和高增益低压运算放大器。相比混合模式（器件-电路）仿真，所提出的基于LUT的方法被证明是更快，从而使它实际上是一个可行的和有吸引力的选择，特别是对于新兴技术的可变性分析紧凑的模型是不可用的电路仿真。
This paper presents a novel table-based approach for efficient statistical analysis of Finfield effect transistor circuits. The proposed approach uses a new scheme for interpolation of look-up tables (LUTs) with respect to process parameters. The effect of various process parameters, viz., channel length, fin width, and effective oxide thickness is studied for three circuits: buffer chain, static random access memory cell, and high-gain low-voltage op-amp. Compared to mixed-mode (device-circuit) simulation, the proposed LUT-based approach is shown to be much faster, thus making it practically a feasible and attractive option for variability analysis especially for emerging technologies where compact models are not available for circuit simulation.