Poly Gate Proximity Effect Modeling for 40nm CMOS
Poly Gate Proximity Effect Modeling for 40nm CMOS
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DOI：
10.4028/www.scientific.net/amm.236-237.134
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发表时间：
2012-11
期刊：
影响因子：
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通讯作者：
Xi Li;Zheng Ren;Ming Wang;Hui Zhou;Li Jie Sun;ShaoJian Hu;Yanling Shi
中科院分区：
文献类型：
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作者：
Xi Li;Zheng Ren;Ming Wang;Hui Zhou;Li Jie Sun;ShaoJian Hu;Yanling Shi
提出了一种新的用于描述40 nmCMOSFET多晶硅栅邻近效应的psp模型。该模型考虑了栅间距和相邻栅数目对迁移率和平带电压的影响。通过硅片验证，所建模型可模拟饱和电流变化达5%-7%，平带电压变化达6- 8 mv。还监测Vthlin、Idlin和Gmmax。这些良好的结果显示了新模型在先进CMOS节点电路设计中的重要性。
A new compact and scalable psp model for the layout proximity effect of poly gate in 40nm CMOSFET is proposed. This model takes into account the impact of gate space and neighboring gates number on mobility and flatband voltage. With the silicon verification, saturation current change up to 5%–7% and flatband voltage change up to 6-8mv is modeled in the constructed model. Vthlin, Idlin and Gmmax are also monitored. These good results show the importance of the new model for circuit design in advanced CMOS node.