Quantifying the Capacity Gains in Coarsely Quantized SISO Systems with Nonlinear Analog Operators
Quantifying the Capacity Gains in Coarsely Quantized SISO Systems with Nonlinear Analog Operators
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DOI：
10.1109/gcwkshps56602.2022.10008530
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发表时间：
2022-08
期刊：
影响因子：
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通讯作者：
Farhad Shirani;Hamidreza Aghasi
中科院分区：
文献类型：
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作者：
Farhad Shirani;Hamidreza Aghasi
高速、高分辨率模数转换器(ADC)的功耗是实现大带宽毫米波通信系统的限制因素。最近引起了相当大兴趣的一种缓解方案是在接收器上使用几个低分辨率ADC。虽然减少ADC的数目和分辨率降低了功耗，但由于粗量化导致的信息丢失，这也导致了信道容量的减少。这意味着由ADC的数量和分辨率控制的速率-能量权衡。最近的研究表明，在给定固定数目的低分辨率模数转换器的情况下，在采样和量化之前应用实际可实现的非线性模拟算子可以显著降低上述速率损失。在此基础上，本文研究了单输入单输出(SISO)通信场景，刻画了在可实现的非线性模拟函数集上的各种假设下的容量表达式，提供了数值计算信道容量的方法，以及iii)量化了由于在SISO接收终端中使用非线性算子而产生的增益。此外，使用65 nm体硅工艺进行了电路级模拟，以显示所需的非线性算子在模拟域中的可实现性。针对不同的模拟操作员，对所提出的电路的功率需求进行了量化。
The power consumption of high-speed, high-resolution analog to digital converters (ADCs) is a limiting factor in implementing large-bandwidth mm-wave communication systems. A mitigating solution, which has drawn considerable recent interest, is to use a few low-resolution ADCs at the receiver. While reducing the number and resolution of the ADCs decreases power consumption, it also leads to a reduction in channel capacity due to the information loss induced by coarse quantization. This implies a rate-energy tradeoff governed by the number and resolution of ADCs. Recently, it was shown that given a fixed number of low-resolution ADCs, the application of practically implementable nonlinear analog operators, prior to sampling and quantization, may significantly reduce the aforementioned rate-loss. Building upon these observations, this work focuses on single-input single-output (SISO) communication scenarios, and i) characterizes capacity expressions under various assumptions on the set of implementable nonlinear analog functions, ii) provides computational methods to calculate the channel capacity numerically, and iii) quantifies the gains due to the use of nonlinear operators in SISO receiver terminals. Furthermore, circuit-level simulations, using a 65 nm Bulk CMOS technology, are provided to show the implementability of the desired nonlinear operators in the analog domain. The power requirements of the proposed circuits are quantified for various analog operators.