Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems
Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems
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DOI：
10.1145/2818950.2818951
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发表时间：
2015-10
期刊：
影响因子：
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通讯作者：
G. Loh;Natalie D. Enright Jerger;Ajaykumar Kannan;Yasuko Eckert
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文献类型：
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作者：
G. Loh;Natalie D. Enright Jerger;Ajaykumar Kannan;Yasuko Eckert
硅插入器技术有望在处理器封装中实现存储器的大规模集成。虽然过去在垂直、3D堆叠内存方面的研究允许将一堆内存直接放置在处理器的顶部，但可以集成的内存总量受到处理器芯片大小的限制。使用硅插入器，可以在处理器封装内集成多个存储器堆栈，从而增加3D存储器提供的容量和带宽。然而，如果封装内互连体系结构不能跟上由多个存储器堆栈提供的数据速率，则所有这种集成存储器的全部潜力可能被浪费。这份立场文件描述了为基于插入器的主动存储器集成提供互连支持的关键问题，并主张进行更多的研究工作来解决这些挑战，使集成存储器能够充分发挥其价值。
Silicon interposer technology is promising for large-scale integration of memory within a processor package. While past work on vertical, 3D-stacked memory allows a stack of memory to be placed directly on top of a processor, the total amount of memory that could be integrated is limited by the size of the processor die. With silicon interposers, multiple memory stacks can be integrated inside the processor package, thereby increasing both the capacity and the bandwidth provided by the 3D memory. However, the full potential of all of this integrated memory may be squandered if the in-package interconnect architecture cannot keep up with the data rates provided by the multiple memory stacks. This position paper describes key issues in providing the interconnect support for aggressive interposer-based memory integration, and argues for additional research efforts to address these challenges to enable integrated memory to deliver its full value.