Electrical features of the metal-thin porous silicon-silicon structure
Electrical features of the metal-thin porous silicon-silicon structure
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DOI：
10.1088/0022-3727/33/16/304
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发表时间：
2000-08
期刊：
影响因子：
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通讯作者：
V. Vikulov;V. Strikha;V. Skryshevsky;S. Kilchitskaya;É. Souteyrand;J. R. Martin
中科院分区：
文献类型：
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作者：
V. Vikulov;V. Strikha;V. Skryshevsky;S. Kilchitskaya;É. Souteyrand;J. R. Martin
本文考虑了金属-隧道界面层-薄多孔硅-p-Si结构的理论模型。在适当的边界条件下求解扩散-漂移方程，以阐明载流子的输运机制。在静电感应矢量连续的条件下，通过求解该方程，计算了沿结构的电压降分布。得到的解析表达式使人们能够分析界面层、多孔硅和表面电子态对结构电学行为的贡献。通过对不同多孔硅层厚度的Pd-多孔硅(孔隙率为60%)-p-Si结构的实验I-V特性和C-V特性与理论值的比较，确定了模型的一些参数。定义势垒高度e0的范围为0.45~0.47 eV，界面层主要由达到3.0 nm的本征氧化物组成，与电化学刻蚀时间无关。通过对实验的高频C-V曲线和稳态I-V曲线的比较，得到了表面电子态部分电压下降的证据。多孔硅层的增厚导致表面电子态的能带移动。
This paper considers a theoretical model of the metal-tunnel interface layer-thin porous silicon-p-Si structure. A diffusion-drift equation at the appropriate boundary conditions is solved to clarify a mechanism of the carriers' transport. The voltage drop distribution along the structure is calculated by solving the equations under the condition of continuity of the vector of the electrostatic induction. The obtained analytical expressions allow one to analyse the contribution of the interface layer, porous silicon and surface electron states to the electrical behaviour of the structure. Some parameters of the model are defined from the comparison of experimental I-V and C-V characteristics with theoretical values for the Pd-porous silicon (60% of porosity)-p-Si structures having different thicknesses of porous silicon layers. The defined barrier height e0 ranged from 0.45 to 0.47?eV, the interface layer consisted of mainly the native oxide achieved up to 3.0?nm and did not depend on the time of Si electrochemical etching. The evidence that part of the voltage drops on the surface electron states is ensued by comparing the experimental high frequency C-V curves with steady-state I-V curves. Thickening of the porous silicon layer results in a shift in the energetic band of the surface electronic states.