A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation
A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation
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具有列 MAC 架构和位串行计算功能的 1-16b 精密可重配置数字内存计算宏
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发表时间：
2019
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通讯作者：
Bongjin Kim
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作者：
Hyunjoon Kim;Qian Chen;Taegeun Yoo;T. T. Kim;Bongjin Kim
这项工作提出了一个具有1-16b可重构权重和输入位精度的数字内存计算宏，用于节能深度神经网络处理。所提出的数字宏包括128×128位单元，每个位单元由三个用于内存计算的构建块、一个基于xnor的位乘法器、一个全加法器和一个SRAM单元组成。然后将二维位单元数组划分为并行神经元，每个神经元具有排成一行的128×柱状乘法和累加（column-MAC）单元。每个具有N位可变权重精度的列mac都在列中使用“N+7”位元（即1- 16位的8- 23位元）构建。n位权重存储在SRAM单元中，用于内存计算，获取权重的内存访问最少。剩余的7位单元格用于扩展msb，以便通过128列mac累积部分和。将位串行输入广播到同一列中的所有位单元格，并执行并行的按位相乘操作。每个列mac的按位相乘结果然后使用N+7个全加法器累积，这些加法器垂直连接以作为纹波进位加法器。同时，输入精度由LSB到MSB的位串行输入周期数决定。因此，需要多比特输入精度的后累加。制作了65nm测试芯片，测得1-16bit时的能量效率为117.3 ~ 2.06TOPS/W。
This work proposes a digital in-memory computing macro with 1-16b reconfigurable weight and input bit-precisions for energy-efficient DNN processing. The proposed digital macro comprises 128×128 bitcells, and each bitcell consists of three building blocks for in-memory computing, an XNOR-based bitwise multiplier, a full-adder, and an SRAM cell. The two-dimensional bitcell array is then divided into parallel neurons, each with 128× column-shape multiply-and-accumulate (column-MAC) units arranged in a row. Each column-MAC with N-bit variable weight precision is built with ‘N+7’ bitcells in a column (i.e., 8-to-23 bitcells at 1-to-16bit). The N-bit weights are stored at SRAM cells for in-memory computing with the minimal memory access for fetching weights. The remaining 7 bitcells are needed to extend MSBs for accumulating partial-sums through 128 column-MACs. A bit-serial input is broadcasted to all bitcells in the same column, and parallel bitwise multiply operations are performed. Bitwise multiplied results from each column-MAC are then accumulated using N+7 full-adders which are vertically connected to work as a ripple carry adder. Meanwhile, the input precision is determined by the number of bit-serial input cycles from LSB to MSB. Hence, the post-accumulation is required for multi-bit input precision. A 65nm test-chip is fabricated, and the measured energy-efficiency is 117.3 to 2.06TOPS/W at 1-16bit.