A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB
A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB
复制标题
最坏情况 FOM 为 160 dB 的可重新配置的全数字 Delta-Sigma ADC
DOI：
10.1109/jssc.2013.2239113
复制
发表时间：
2013
影响因子：
5.4
通讯作者：
I. Galton
中科院分区：
文献类型：
--
作者：
Gerry Taylor;I. Galton
本文提出了一种基于压控环形振荡器（VCO）的第二代大部分数字背景校准过采样ADC。它的性能与迄今为止发布的最佳Δ μ m调制器ADC一致，但它占用的电路面积要小得多，可重新配置，并且主要由数字电路组成。相对于第一代版本的增强功能包括VCRO中的数字背景校准开环V / I转换，以增加ADC带宽并支持单低压电源供电;正交耦合环形振荡器，以降低量化噪声;数字超量程校正，以提高动态范围并实现适度过载行为;以及各种电路级改进。该ADC采用65 nm CMOS工艺，占地0.075 mm 2，采用0.9-1.2 V单电源供电。其采样率在1.3 ~ 2.4GHz范围内可调，SNDR范围为70- 75dB，带宽范围为5 ~ 37.5MHz，最小SNDR+10 log（带宽/功耗）优值（FOM）为160 dB。
This paper presents a second-generation mostly-digital background-calibrated oversampling ADC based on voltage- controlled ring oscillators (VCROs). Its performance is in line with the best ΔΣ modulator ADCs published to date, but it occupies much less circuit area, is reconfigurable, and consists mainly of digital circuitry. Enhancements relative to the first-generation version include digitally background-calibrated open-loop V / I conversion in the VCRO to increase ADC bandwidth and enable operation from a single low-voltage power supply, quadrature coupled ring oscillators to reduce quantization noise, digital over-range correction to improve dynamic range and enable graceful overload behavior, and various circuit-level improvements. The ADC occupies 0.075 mm2 in a 65 nm CMOS process and operates from a single 0.9-1.2 V supply. Its sample-rate is tunable from 1.3 to 2.4 GHz over which the SNDR spans 70-75 dB, the bandwidth spans 5-37.5 MHz, and the minimum SNDR+ 10log(bandwidth/power dissipation) figure of merit (FOM) is 160 dB.