System-level Evaluation of Chip-Scale Silicon Photonic Networks for Emerging Data-Intensive Applications
System-level Evaluation of Chip-Scale Silicon Photonic Networks for Emerging Data-Intensive Applications
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DOI：
10.23919/date48585.2020.9116496
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发表时间：
2020-03
期刊：
影响因子：
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通讯作者：
A. Narayan;Y. Thonnart;P. Vivet;A. Joshi;A. Coskun
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文献类型：
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作者：
A. Narayan;Y. Thonnart;P. Vivet;A. Joshi;A. Coskun
新兴的数据驱动的应用程序，如图形处理应用程序的特点是其过多的内存占用和丰富的并行性，导致高内存带宽的需求。随着应用程序的数据集规模达到TB数量级，带宽需求导致的性能限制是一个主要问题。传统的片上电网络由于增加的每比特能量或引脚数的物理限制而无法满足这样的高带宽需求。硅光子网络由于其高带宽密度和每比特低能量通信以及可忽略的数据依赖功率而成为电互连的有前途的替代方案。然而，芯片级硅光子学的大规模采用受到其对工艺和热变化的高灵敏度、由于沿着网络的损耗而导致的高激光功率以及电光转换的功耗的阻碍。设备级技术创新，以减轻这些问题是有前途的，但他们没有考虑系统级的应用程序运行在多核系统与光子网络的影响。这项工作旨在弥合应用程序的系统级属性与硅光子网络的底层架构和设备级特性之间的差距，以实现节能计算。我们特别关注图形应用程序，其中涉及非结构化但丰富的并行存储器访问，强调片上通信网络，并开发一个跨层框架，以评估2.5D系统与硅光子网络。我们展示了38%的功率节省，通过系统级管理使用波长选择政策，只有1%的系统性能损失，并进一步评估2.5D系统与光子网络的架构设计选择。
Emerging data-driven applications such as graph processing applications are characterized by their excessive memory footprint and abundant parallelism, resulting in high memory bandwidth demand. As the scale of datasets for applications is reaching orders of TBs, performance limitation due to bandwidth demands is a major concern. Traditional on-chip electrical networks fail to meet such high bandwidth demands due to increased energy-per-bit or physical limitations with pin counts. Silicon photonic networks have emerged as a promising alternative to electrical interconnects, owing to their high bandwidth density and low energy-per-bit communication with negligible data-dependent power. Wide-scale adoption of silicon photonics at chip level, however, is hampered by their high sensitivity to process and thermal variations, high laser power due to losses along the network, and power consumption of the electrical-optical conversion. Device-level technological innovations to mitigate these issues are promising, yet they do not consider the system-level implications of the applications running on manycore systems with photonic networks. This work aims to bridge the gap between the system-level attributes of applications with the underlying architectural and device-level characteristics of silicon photonic networks to achieve energy-efficient computing. We particularly focus on graph applications, which involve unstructured yet abundant parallel memory accesses that stress the on-chip communication networks, and develop a cross-layer framework to evaluate 2.5D systems with silicon photonic networks. We demonstrate 38% power savings through system-level management using wavelength selection policies with only 1% loss in system performance and further evaluate architectural design choices on 2.5D systems with photonic networks.