Spin-based logic in semiconductors for reconfigurable large-scale circuits
Spin-based logic in semiconductors for reconfigurable large-scale circuits
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DOI：
10.1038/nature05833
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发表时间：
2007-05-31
期刊：
影响因子：
64.8
通讯作者：
Sham, L. J.
中科院分区：
文献类型：
--
作者：
Dery, H.;Dalal, P.;Sham, L. J.
半导体自旋电子学的研究旨在通过使用电子的自旋自由度以及其电荷来扩展传统电子学的范围（1）。在这一领域的重大科学进展已被报道，如稀释铁磁半导体的发展（2，）3，自旋注入半导体从铁磁金属（4-8）和发现新的物理现象，涉及电子自旋（9，10）。然而，还没有提出在半导体中发展自旋电子学的可行方法。在这里，我们报告了一个理论设计，这是一个概念性的一步向前自旋积累被用作半导体计算机电路的基础。虽然金属（11，12）中的巨磁电阻效应已经被商业开发，但它没有扩展到半导体/铁磁体系统，因为该效应对于逻辑运算来说太弱。我们通过使用自旋积累而不是自旋流来克服这个障碍（13-15）。在我们的设计中的基本元素是一个逻辑门，由一个半导体结构与多个磁性触点;这有助于在嘈杂的，室温环境中执行快速和可重新编程的逻辑运算。然后，我们介绍了一种方法来互连大量的这些门，形成一个“自旋计算机”。随着传统互补金属氧化物半导体（CMOS）晶体管的缩小达到其固有极限，更大的计算能力将意味着电路面积和功耗的增加。我们的自旋为基础的方法可以提供更宽的利润进一步缩放，也更大的计算能力，每门。
Research in semiconductor spintronics aims to extend the scope of conventional electronics by using the spin degree of freedom of an electron in addition to its charge(1). Significant scientific advances in this area have been reported, such as the development of diluted ferromagnetic semiconductors(2,)3, spin injection into semiconductors from ferromagnetic metals(4-8) and discoveries of new physical phenomena involving electron spin(9,10). Yet no viable means of developing spintronics in semiconductors has been presented. Here we report a theoretical design that is a conceptual step forward-spin accumulation is used as the basis of a semiconductor computer circuit. Although the giant magnetoresistance effect in metals(11,12) has already been commercially exploited, it does not extend to semiconductor/ ferromagnet systems, because the effect is too weak for logic operations. We overcome this obstacle by using spin accumulation rather than spin flow(13-15). The basic element in our design is a logic gate that consists of a semiconductor structure with multiple magnetic contacts; this serves to perform fast and reprogrammable logic operations in a noisy, room-temperature environment. We then introduce a method to interconnect a large number of these gates to form a 'spin computer'. As the shrinking of conventional complementary metal-oxide-semiconductor (CMOS) transistors reaches its intrinsic limit, greater computational capability will mean an increase in both circuit area and power dissipation. Our spin-based approach may provide wide margins for further scaling and also greater computational capability per gate.