Development of a low power 5.12 Gbps data serializer and wireline transmitter circuit for the VeloPix chip
Development of a low power 5.12 Gbps data serializer and wireline transmitter circuit for the VeloPix chip
复制标题
为 VeloPix 芯片开发低功耗 5.12 Gbps 数据串行器和有线发送器电路
DOI：
--
复制
发表时间：
2015
期刊：
影响因子：
--
通讯作者：
K. Wyllie
中科院分区：
文献类型：
--
作者：
V. Gromov;V. Zivkovic;M. Beuzekom;X. Llopart;T. Poikela;J. Buytaert;M. Gaspari;M. Campbell;K. Wyllie
在计划于2018年进行升级后，正在开发一种新的前端芯片(VeloPix)，用于读出LHCb实验中的硅顶点定位器探测器(Velo)。该芯片的有效面积为2平方厘米，将以非常高的命中率(高达500Mhitcm−2秒−1)运行，并将通过1米低质量铜缆传输大量数据(>；15 Gbit/秒)。以5.12Gbps数据串行器和有线发送器(线路驱动器)电路为原型的测试芯片已经提交，采用130 nm CMOS工艺。串行化模块的实现采用了基于多路复用器的体系结构。在所提出的解决方案中，16比1循环多路复用器从时钟频率为320 MHz的16位输入寄存器的后边缘触发部分或负边缘触发部分中一次选择一位数据。串行器的功耗仅为15 mW，预加重的线路驱动器的功耗为45 mW。文中对该电路的设计进行了说明，并给出了部分测试结果。
A new front-end chip (VeloPix) is being developed for the readout of the silicon vertex locator detector (VELO) in the LHCb experiment after the upgrade scheduled for 2018. The chip with an active area of 2 cm2 will run at a very high hit rate (up to 500 Mhitcm−2sec−1) and will transmit large amounts of data (> 15 Gbit-per-sec) over a 1 meter low-mass copper cable. A test chip with a prototype of a 5.12 Gbps Data Serializer and Wireline Transmitter (line driver) circuit has been submitted in 130 nm CMOS technology. A multiplexer based architecture has been chosen for the implementation the serializer block. In the proposed solution a 16-to-1 round-robin multiplexer selects one bit of data at a time from either a posedge triggered section or a negedge triggered section of a 16-bit input register clocked at 320 MHz. The serializer consumes only 15 mW of power and the line driver with pre-emphasis consumes 45 mW. In this paper the circuit design is explained and some measured results are presented.