Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay
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基于仿真的框架，用于准确估计动态电源噪声和路径延迟
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
C. Patel
中科院分区：
文献类型：
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作者：
S. K. Rao;R. Robucci;C. Patel
在亚微米设计中，电源噪声是导致成品率损失的主要因素之一。在测试模式下过度切换会导致电源电压比在功能模式下下降得更多，从而导致延迟测试失败，而这在正常操作下是不会发生的。因此，需要在设计阶段早期准确估计片上电源噪声，以满足正常模式和测试期间的功率要求，以防止测试周期中的过度刺激并避免错误故障。多个逻辑元件的同时开关活动(SSA)是导致逻辑门电源电压降低的电源噪声(PSN)的主要来源之一。大多数现有的技术和工具预测静态IR降，它只占电网总电压降的一部分。据我们所知，为简化起见，目前的噪声分析中没有考虑感应降噪。今天的极深亚微米芯片中的功率传输网络容易受到微小变化的影响，并导致突然的大电流尖峰，导致比阻性下降更高的LDI⁄DT，这就需要考虑这种下降。电源噪声还会影响电路运行，导致路径延迟显著增加。然而，在设计上进行全芯片SPICE级模拟以验证ATPG生成的测试码是不可行的。需要准确和高效的技术来量化电源噪声及其对路径延迟的影响，以确保在任务模式和测试期间都能可靠运行。我们提出了一种可扩展的基于电流的动态方法来估计由同时开关活动引起的IR和LDI/DT下降，并使用该技术来预测路径延迟的增加。与耗时的全芯片模拟相比，我们的技术使用单个提取路径的模拟，因此它可以与现有的ATPG工具集成。该方法使用这些路径模拟和基于卷积的技术来估计电源噪声和路径延迟。给出了组合基准电路和顺序基准电路的仿真结果，证明了该方法的有效性。
Power-supply noise is one of the major contributing factor for yield loss in sub-micron designs. Excessive switching in test mode causes supply voltage to droop more than in functional mode leading to failures in delay tests that would not occur otherwise under normal operation. Thus, there exists a need to accurately estimate on-chip supply noise early in the design phase to meet power requirements in normal mode and during test to prevent overstimulation during the test cycle and avoid false failures. Simultaneous switching activity (SSA) of several logic components is one of the main sources of power-supply noise (PSN) which results in reduction of supply voltages at the power-supplies of the logic gates. Most existing techniques and tools predict static IR-drop, which accounts for only part of the total voltage drop on the power grid. To our knowledge, inductive drop is not included in current noise analysis for simplification. The power delivery networks in today’s very deep-submicron chips are susceptible to slight variations and cause sudden large current spikes leading to higher Ldi ⁄ dt than resistive drop essentiating the need to account for this drop. Power-supply noise also impacts circuit operation incurring a significant increase in path delays. However, it is infeasible to carry out full-chip SPICE-level simulations on a design to validate the ATPG generated test patterns. Accurate and efficient techniques are required to quantify supply noise and its impact on path delays to ensure reliable operation in both mission mode and during test. We present a scalable current-based dynamic method to estimate both IR and Ldi / dt drop caused by simultaneous switching activity and use the technique to predict the increase in path delay. Our technique uses simulations of individual extracted paths in comparison to time-consuming full-chip simulations and thus it can be integrated with existing ATPG tools. The method uses these path simulations and a convolution-based technique to estimate power-supply noise and path delays. Simulation results for combinational and sequential benchmark circuits are presented demonstrating the effectiveness of our techniques.