Modeling of Drain Electric Flux Passing Through the BOX Layer in SOI MOSFETs-Part II: Model Derivation and Validity Confirmation
Modeling of Drain Electric Flux Passing Through the BOX Layer in SOI MOSFETs-Part II: Model Derivation and Validity Confirmation
复制标题
SOI MOSFET 中穿过 BOX 层的漏极电通量建模 - 第二部分：模型推导和有效性确认
DOI：
10.1109/ted.2014.2340900
复制
发表时间：
2014
影响因子：
3.1
通讯作者：
and T. Toyabe
中科院分区：
文献类型：
--
作者：
T. Yamada. T. Hanajiri;and T. Toyabe
Increased drain-induced barrier lowering caused by drain electric flux (or field) passing through the buried-oxide (BOX) layer in silicon-on-insulator (SoI) MOSFETs has been reported as an inherent disadvantage of SoI technology. Part I of this paper discussed derivation of the relationships between coordinates in MOSFETs and potential/stream function in preparation for the modeling of electric flux using conformal mapping in subthreshold regions of ground plane SoI MOSFETs and the validity of the approach was checked via device simulation. Here, in Part II of this paper, we discussed the model's derivation based on these relationships. The dependences of the flux amount on BOX thickness, BOX permittivity, SoI thickness, and gate length estimated using the model were also discussed in comparison with those estimated via device simulation.
