FPGA-based latency-insensitive OFDM pipeline for wireless research
FPGA-based latency-insensitive OFDM pipeline for wireless research
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DOI：
10.1109/hpec.2014.7040969
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发表时间：
2014-09
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通讯作者：
James Chacko;Cem Sahin;D. Nguyen;Doug Pfeil;Nagarajan Kandasamy;K. Dandekar
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作者：
James Chacko;Cem Sahin;D. Nguyen;Doug Pfeil;Nagarajan Kandasamy;K. Dandekar
本文开发了一种基于正交频分复用（OFDM）的认知无线通信系统物理层的可编程硬件实现。所有通信标准的硬件实现基带架构内的数据流本质上是相当规则的，因此可以在fpga上构建快速，同步和优化的基带系统。我们设计了一个OFDM管道，包括编解码、调制、交错、导频、信道估计和IFFT阶段，其中每个阶段都可以在设计时或运行时配置，以适应不同的通信标准以及单个标准的不同配置设置——这是动态频谱感知和利用所必需的关键特征。硬件上的这种灵活性是通过为每个单独的阶段设计有扩展/修改的空间，并使整个管道对单个管道阶段产生的延迟不敏感来实现的。这是通过使用可安装阶段和集中控制来实现的，通过模块之间的交叉通信，直接或间接地使用在MicroBlaze处理器上运行的代码。OFDM管道在Xilinx Virtex-6 FPGA上实现，其性能从功能正确性和FPGA实现面积成本两方面进行了表征。实验结果和初步仿真表明，基于FPGA的设计可以在1/2和3/4的灵活编码速率下运行，调制方案分别为4QAM和16QAM。
This paper develops a programmable hardware implementation of the physical layer for cognitive wireless communication systems that use orthogonal frequency division multiplexing (OFDM) schemes. Data-flows within hardware implemented baseband architectures for all communication standards are quite regular in nature, thereby enabling the construction of fast, synchronized and optimized baseband systems on FPGAs. We designed an OFDM pipeline comprising codec, modulation, interleaving, piloting, channel estimation, and IFFT stages in which each stage can be configured at design time or at run time to accommodate different communication standards as well as different configuration settings for a single standard-a key feature necessary for dynamic spectrum sensing and utilization. This flexibility in hardware is achieved by designing each individual stage with room for scaling/modification and having the overall pipeline be insensitive to the latencies incurred by individual pipeline stages. This is done by using stallable stages with centralized control through cross communication between modules both directly and indirectly using code running on the MicroBlaze processor. The OFDM pipeline is implemented on a Xilinx Virtex-6 FPGA and its performance is characterized in terms of functional correctness and FPGA implementation area cost. Experimental results and preliminary simulations of our FPGA based design can run at flexible coding rates of 1/2 and 3/4 with modulation schemes of 4QAM and 16QAM respectively.