A fully integrated two-channel A/D interface for the acquisition of cardiac signals in implantable pacemakers
A fully integrated two-channel A/D interface for the acquisition of cardiac signals in implantable pacemakers
复制标题
DOI：
10.1109/jssc.2004.829921
复制
发表时间：
2003-09
影响因子：
5.4
通讯作者：
A. Gerosa;Andrea Maniero;A. Neviani
中科院分区：
文献类型：
--
作者：
A. Gerosa;Andrea Maniero;A. Neviani
这项工作为心脏起搏器提供了一个输入级，该起搏器完全集成在0.35/SPL mU/m CMOS工艺中。该系统可以采集和数字化8位的房室电活动。采用对数域电路对输入信号进行放大和滤波，采用/SPL Sigma//SPL Delta/调制法对输入信号进行转换。该设计经过了功耗优化，电流消耗限制在2.9个/splµ/A以内，电源电压范围为2.8~1.8V，总面积为2.2 mm/sup2/，实验数据证明滤波正确，总动态范围至少为47分贝。
This work presents an input stage for a cardiac pacemaker fully integrated in 0.35-/spl mu/m CMOS technology. The system can acquire and digitize to 8 bits both atrial and ventricular electrical activity. Log-domain circuits are exploited to amplify and filter the input signal, while /spl Sigma//spl Delta/ modulation is exploited to convert it. The design is power optimized, indeed the current consumption is limited to 2.9 /spl mu/A, while the power supply ranges from 2.8 to 1.8 V. The total area is 2.2 mm/sup 2/ and experimental data prove correct filtering and a total dynamic range of at least 47 dB.