Boolean and Sequential Logic in a One‐Memristor‐One‐Resistor (1M1R) Structure for In‐Memory Computing
Boolean and Sequential Logic in a One‐Memristor‐One‐Resistor (1M1R) Structure for In‐Memory Computing
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DOI：
10.1002/aelm.201800229
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发表时间：
2018-06
影响因子：
6.2
通讯作者：
Yaxiong Zhou;Yi Li;Nian Duan;Zhuorui Wang;K. Lu;Miao‐Miao Jin;Long Cheng;Si-Yu Hu;T. Chang;Huajun Sun;K. Xue;X. Miao
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文献类型：
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作者：
Yaxiong Zhou;Yi Li;Nian Duan;Zhuorui Wang;K. Lu;Miao‐Miao Jin;Long Cheng;Si-Yu Hu;T. Chang;Huajun Sun;K. Xue;X. Miao
忆阻器件作为高性能的内存计算结构，已经引起了非易失性并行架构的广泛关注，以打破冯诺依曼瓶颈。在这里，首次提出了具有三端Pt/SiO2/Pt/Ag/GeTe/Ta单忆阻器单电阻（1 M1 R）结构的非易失性数字逻辑系统。实验实现了可编程非易失性布尔逻辑门和时钟时序逻辑模块，包括D锁存器和D触发器，并在此基础上仿真验证了具有时序设计的4位线性反馈移位寄存器的功能。随着信息的生成、处理、传输和存储在相同的基于1 M1 R的逻辑块中执行，这些结果巩固了为未来的非冯·诺依曼计算构建忆阻数字计算系统的可行性。
Memristive devices acting as high‐performance in‐memory computing fabrics have attracted much attention for nonvolatile parallel architectures to break the von Neumann bottleneck. Here, for the first time, a nonvolatile digital logic system with three‐terminal Pt/SiO2/Pt/Ag/GeTe/Ta one‐memristor‐one‐resistor (1M1R) structure is presented. Programmable nonvolatile Boolean logic gates and clocked sequential logic blocks including D latch and D flip‐flop are experimentally implemented, based on which a 4‐bit linear‐feedback shift register with timing design is functionally verified in simulation. With information generation, processing, transmission, and storage performing within the same 1M1R‐based logic blocks, these results consolidate the feasibility of building memristive digital computing system for future non‐von Neumann computing.