Cs-Corrected STEM Observation and Atomic Modeling of Grain Boundary Impurities of Very Narrow Cu Interconnect
Cs-Corrected STEM Observation and Atomic Modeling of Grain Boundary Impurities of Very Narrow Cu Interconnect
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DOI：
10.1149/2.001306eel
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发表时间：
2013
影响因子：
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通讯作者：
T. Nagano;Kunihiro Tamahashi;Y. Sasajima;J. Onuki
中科院分区：
文献类型：
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作者：
T. Nagano;Kunihiro Tamahashi;Y. Sasajima;J. Onuki
如果我们能够在退火过程中明确杂质的种类以及杂质在晶粒生长过程中的作用，我们就可以通过去除电镀材料中的上述有害杂质来控制晶粒尺寸分布，从而实现极低电阻率和高电迁移性的Cu互连，为未来的高速低功耗lsi提供支持。因此，在纳米尺度上分析晶界上的偏析元素和了解偏析机制是必不可少的。在本研究中，我们直接观察到晶界处的杂质偏析是由比埋在沟槽中的Cu多晶互连更轻的元素组成的。我们还用从头算法计算了所观察到的元素的偏析能。采用电子束光刻和反应离子刻蚀技术在二氧化硅介质薄膜上刻制了宽度为80 ~ 100 nm、高度为200 nm、长度为1 mm的四点探针几何沟槽，以及四个高度相同的200 μm方形衬垫。依次溅射沉积超薄TaN/Ta （TaN:7.5 nm; Ta:7.5 nm）和50 nm的种子层，如图1所示。之后是8英寸。硅片被切成10毫米见方的薄片用于电镀。镀液中含有0.63 mol/dm 3标称3N CuSO4·5H2O、0.105 mol/dm 3 H2SO4和3.7 × 10−3 mol/dm 3 HCl。所需的有机促进剂、有机抑制剂和匀平剂添加剂也被添加到镀液中。使用的阳极板
If we can clarify the kinds of impurities, and the role of impurities in the grain growth process during annealing, we could control grain size distributions by removal of above harmful impurities from electroplating materials leading to the realization of very low resistivity and high electro-migration resistant Cu interconnects for future high speed and low electric power consumption LSIs. Therefore, nanoscale analysis of the segregated elements at the grain boundary and understanding of the segregation mechanism are indispensable. In this study, we directly observed the segregation of impurities at the grain boundary consist of lighter elements than Cu polycrystal interconnects buried in trench using Cs-corrected STEM. We also calculated the segregation energies using ab initio method for the observed elements. Trenches in a four-point probe geometry of 80‐100 nm width, with 200 nm height and 1 mm length, and four 200 μm square pads with the same height were patterned in silicon dioxide dielectric films using electron beam lithography and reactive ion etching. Ultrathin TaN/Ta (TaN:7.5 nm; Ta:7.5 nm) and a 50 nm seed layer were sputterdeposited in that order as shown in Fig. 1. After that, an 8 in. wafer was cut into 10 mm square chips for the electroplating. The plating solution contained 0.63 mol/dm 3 nominal 3N CuSO4 ·5H2O, 0.105 mol/dm 3 H2SO4, and 3.7 × 10 −3 mol/dm 3 HCl. The required organic accelerator, organic suppressor, and leveler additives were also added to the plating solution. The anode plate used