Process-strained Si (PSS) CMOS technology featuring 3D strain engineering
Process-strained Si (PSS) CMOS technology featuring 3D strain engineering
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DOI：
10.1109/iedm.2003.1269169
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发表时间：
2003-12
期刊：
影响因子：
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通讯作者：
C. Ge;C.C. Lin;C. Ko;C.C. Huang;Y. Huang;B. Chan;B.-C. Perng;C. Sheu;Pang-Yen Tsai;L. Yao;C.-L. Wu;T. Lee;C. Chen;C. Wang;S.C. Lin;Y. Yeo;C. Hu
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文献类型：
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作者：
C. Ge;C.C. Lin;C. Ko;C.C. Huang;Y. Huang;B. Chan;B.-C. Perng;C. Sheu;Pang-Yen Tsai;L. Yao;C.-L. Wu;T. Lee;C. Chen;C. Wang;S.C. Lin;Y. Yeo;C. Hu
我们报告的过程应变硅（PSS）CMOS技术的演示使用的三维（3D）应变工程的概念。制造PSS的方法包括沟槽隔离、硅化物和帽层的应力工程，以同时改善NMOS和PMOS性能。这些方法中的每一种都导致环形振荡器（RO）速度提高5-10%。通过利用经由一个或组合多个PSS技术的优先3D应变工程，可以进一步提高CMOS性能。PSS是一种符合CMOS功耗性能要求的高性价比技术。
We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, silicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.