Analysis of Metastable Operation in a CMOS Dynamic D-Latch
Analysis of Metastable Operation in a CMOS Dynamic D-Latch
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CMOS 动态 D 锁存器中的亚稳态操作分析
DOI：
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发表时间：
1997
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通讯作者：
José L. Huertas
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作者：
J. Juan;M. Bellido;Antonio J. Acosta;M. Valencia;José L. Huertas
如今，亚稳态已成为高性能VLSI设计中的一个严重问题，主要是由于双稳态电路在高频下工作时相对较高的误差概率。据我们所知，还没有发表任何证明和正式描述动态锁存中的亚稳态行为的著作。在目前的技术条件下，动态锁存器被广泛应用于高性能VLSI电路中，主要是因为它比静态锁存器成本更低，运行速度更快。在这项工作中，我们证明了动态记忆细胞呈现出一种被称为亚稳态操作的异常行为，其特征与静态锁存相似。我们将亚稳态适当地推广到动态情况，并将其应用于CMOS动态d锁存。将提出一个理论模型，允许亚稳态的量化，并将通过HSPICE的电模拟进行验证。然后，我们比较了动态锁存器和静态锁存器的亚稳态行为，得到了两种双稳电路的亚稳态特征参数和平均故障间隔时间（MTBF）的结果。这些结果使我们得出结论，与静态锁存器中的亚稳窗不同，存在一个明确定义的输入间隔，它产生无限的分辨率时间。关于MTBF，与静态闩锁相比，动态闩锁呈现出非常低的MTBF值。这些结果表明，在时钟和数据信号之间的异步风险不可忽略的电路中不应使用动态锁存器。
Nowadays, metastability is becoming a serious problemin high-performance VLSI design, mainly due to the relatively-highprobability of error when a bistable circuit operates at highfrequencies. As far as we know, there is not any work publishedthat justifies and formally characterizes metastable behaviorin dynamic latches. With current technologies, dynamic latchesare widely used in high-performance VLSI circuits, mainly dueto their lower cost and higher operation speed than static latches.In this work, we demonstrate that dynamic memory cells presentan anomalous behavior referred to as metastable operation withcharacteristics similar to those of static latches. We performa suitable generalization of metastability to the dynamic case,applying it to a CMOS dynamic D-latch. A theoretical model willbe proposed, allowing the quantification of metastability, andit will be validated through electric simulation with HSPICE.After that, we have compared the metastable behavior of the dynamiclatch with its static counterpart, obtaining results about thecharacteristic parameters of metastability and the Mean TimeBetween Failures (MTBF) for both kinds of bistable circuits.These results have allowed us to conclude that, unlike metastabilitywindows in static latches, a clearly defined input interval existswhich produces an infinite resolution time. Regarding MTBF, thedynamic latch presents a very low MTBF value compared to thestatic latch. These results show that dynamic latches shouldnot be used in those circuits where the risk of asynchronismbetween clock and data signals is not negligible.