On-chip fingerprinting of IC topology for integrity verification
On-chip fingerprinting of IC topology for integrity verification
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用于完整性验证的 IC 拓扑片上指纹识别
DOI：
10.3850/9783981537079_0169
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发表时间：
2016
期刊：
影响因子：
--
通讯作者：
P. Maurine
中科院分区：
文献类型：
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作者：
Maxime Lecomte;J. Fournier;P. Maurine
集成电路（ic）的完整性，特别是用于检测硬件木马（ht）等恶意附加组件的完整性，在最近的几篇研究论文中得到了研究。到目前为止，所提出的技术的主要限制是由工艺变化引起的偏差限制了它们的效率和实用性。这些技术大多比较两个ic的签名，同时试图消除工艺差异。在本文中，我们提出了一种在实践中消除这一限制的新方法。我们首先假设IC感染是在很多层面上完成的，这比在单个电路上完成感染的模型更现实。我们引入了一种不同于测试芯片的CMOS结构在实际设计中的性能变化模型，用于测量工艺变化。该模型用于创建独立于工艺变化的批次签名，并用作定义允许以直接方式检测ht和假冒产品的方法的基础。该模型和方法在30块FPGA板上进行了实验验证。
The integrity of integrated circuits (ICs), in particular for detecting malicious add-ons like Hardware Trojans (HTs), have been studied in several recent research papers. The main limit of the proposed techniques so far is that the bias induced by the process variations restrict their efficiency and practicality. Most of those techniques compare two ICs' signatures while trying to get rid of the process variations. In this paper we propose a novel approach which in practice eliminates this limit. We first make the assumption that IC infection is done at a lot level, which is more realistic than models where infections are done on individual circuits. We introduce a variation model for the performance of CMOS structures in real designs which are different from test chips dedicated to the measure of process variations. This model is used to create signatures of lots which are independent of the process variations and is used as a base to define methods allowing to detect HTs and counterfeits in a straightforward way. The model and the methods are validated experimentally on 30 FPGA boards.