Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs
Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs
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DOI：
10.1007/s11390-013-1367-8
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发表时间：
2013-07
影响因子：
0.7
通讯作者：
N. Xu;Yuchun Ma;Jia Liu;Shou-Chun Tao
中科院分区：
文献类型：
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作者：
N. Xu;Yuchun Ma;Jia Liu;Shou-Chun Tao
为了减少互连延迟并提高芯片性能，随着芯片集成度和芯片功率密度的快速提高，三维（3D）芯片应运而生。因此，由于高功率密度，散热问题是 3D IC 设计的关键挑战之一。多电源电压 (MSV) 技术提供了一种优化功耗的有效方法，从而可以缓解热点问题。但电压分配不仅受到设计性能的限制，而且还受到电路模块物理布局的限制，因为应聚集具有相同电压的模块以减少电源网络布线资源。特别是在 3D 设计中，使用 MSV 技术的优化变得更加复杂，因为高温也会影响路径上的功耗和延迟。在本文中，我们基于混合整数线性规划 (MILP) 模型解决了 3D IC 中 MSV 设计的电压岛生成问题。首先，我们提出了一种用于电压岛生成的通用 MILP 公式，以优化热分布以及电源网络布线资源，同时保持整个芯片的性能。由于火电相互依赖性，提出了一种迭代优化方法来获得收敛。实验结果表明，我们的热感知电压岛生成方法可以在合理的运行时间下将最大片上温度降低 23.64%，并节省电源网络路由资源 16.71%。
To reduce the interconnect delay and improve the chip performance, three-dimensional (3D) chip emerged with the rapid increasing of chip integration and chip power density. Therefore, thermal issue is one of the critical challenges in 3D IC design due to the high power density. Multiple Supply Voltages (MSV) technique provides an efficient way to optimize power consumption which in turn may alleviate the hotspots. But the voltage assignment is limited not only by the performance constraints of the design, but also by the physical layout of circuit modules since the modules with the same voltage should be gathered to reduce the power-network routing resource. Especially in 3D designs, the optimization using MSV technique becomes even more complicated since the high temperature also influences the power consumption and delay on paths. In this paper, we address the voltage-island generation problem for MSV designs in 3D ICs based on a mixed integer linear programming (MILP) model. First, we propose a general MILP formulation for voltage-island generation to optimize thermal distribution as well as power-network routing resources while maintaining the whole chip performance. With the thermal-power interdependency, an iterative optimization approach is proposed to obtain the convergence. Experimental results show that our thermal-aware voltage-island generation approach can reduce the maximal on-chip temperature by 23.64 % with a reasonable runtime and save the power-network routing resources by 16.71 %.