Impact of DM-LRU on WCET: A Static Analysis Approach
Impact of DM-LRU on WCET: A Static Analysis Approach
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DOI：
10.4230/lipics.ecrts.2019.17
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发表时间：
2019-07
期刊：
影响因子：
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通讯作者：
R. Mancuso;H. Yun;I. Puaut
中科院分区：
文献类型：
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作者：
R. Mancuso;H. Yun;I. Puaut
已知现代嵌入式处理器中的缓存记忆可提高平均内存访问性能。不幸的是，他们也众所周知，它们代表了艰苦实时工作量的不可预测性的主要来源。典型缓存的主要局限性之一是内容选择和替换完全在硬件中执行。因此，很难控制软件中的高速缓存行为，而偏爱已知对应用程序最差的执行时间（WCET）产生影响的块的缓存。在本文中，我们考虑了一种缓存替换策略，即DM-LRU，该策略允许系统设计人员优先考虑对已知对应用程序WCET产生重要影响的内存块的缓存。考虑到单核单级高速缓存层次结构，我们描述了基于抽象解释的DM-LRU的时间分析。我们在一个独立的工具包中实施了拟议的分析，并在一组代表性的基准上研究其定性属性。除了使用DM-LRU或类似策略时，除了计算WCET之外，该提出的分析还可以使设计人员可以执行WCET Impact-感知的内容选择内容，以保留在CACHE中。
Cache memories in modern embedded processors are known to improve average memory access performance. Unfortunately, they are also known to represent a major source of unpredictability for hard real-time workload. One of the main limitations of typical caches is that content selection and replacement is entirely performed in hardware. As such, it is hard to control the cache behavior in software to favor caching of blocks that are known to have an impact on an application's worst-case execution time (WCET). In this paper, we consider a cache replacement policy, namely DM-LRU, that allows system designers to prioritize caching of memory blocks that are known to have an important impact on an application's WCET. Considering a single-core, single-level cache hierarchy, we describe an abstract interpretation-based timing analysis for DM-LRU. We implement the proposed analysis in a self-contained toolkit and study its qualitative properties on a set of representative benchmarks. Apart from being useful to compute the WCET when DM-LRU or similar policies are used, the proposed analysis can allow designers to perform WCET impact-aware selection of content to be retained in cache.