Design of a highly reliable, high-speed MTJ-based lookup table circuit using fractured logic-in-memory structure
Design of a highly reliable, high-speed MTJ-based lookup table circuit using fractured logic-in-memory structure
复制标题
使用断裂逻辑内存结构设计高可靠、高速基于 MTJ 的查找表电路
DOI：
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发表时间：
2019
影响因子：
1.5
通讯作者：
T. Hanyu
中科院分区：
文献类型：
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作者：
D. Suzuki;T. Hanyu
提出了一种基于分裂存储逻辑结构的磁隧道结查找表(LUT)电路，该电路结构紧凑，可以同时运行一个多输入LUT电路和多个输入数目较少的LUT电路。由于用于执行组合逻辑功能的复杂NMOS树与读电流路径分离，因此串联连接的NMOS晶体管的电阻大大降低，这使得能够提高读裕度并减小电路延迟。还可以通过增加在具有小面积开销的几个存储单元之间共享的NMOS晶体管的栅宽来改善读取裕度。事实上，与传统电路相比，所提出的六输入LUT电路的读取裕度提高了30.9%。所提出的6输入LUT电路的电路延迟比传统电路小69%。
A magnetic tunnel junction-based lookup table (LUT) circuit based on the fractured logic-in-memory structure, which can operate one multi-input LUT circuit as well as several LUT circuits with a smaller number of inputs with a compact circuitry, is proposed. Since a complex NMOS tree for performing a combinational logic function is separated from a read-current path, the resistance of the series-connected NMOS transistors is greatly reduced, which makes it possible to enhance the read margin and to reduce the circuit delay. The read margin can also be improved by increasing the gate widths of the NMOS transistors that are shared among several memory cells with a small area overhead. In fact, the read margin of the proposed six-input LUT circuits is 30.9% higher compared with that of a conventional circuitry. The circuit delay of the proposed 6-input LUT circuit is 69% smaller the that of the conventional circuitry.