50% active-power saving without speed degradation using standby power reduction (SPR) circuit
50% active-power saving without speed degradation using standby power reduction (SPR) circuit
复制标题
50%%20有功功率%20节省%20无%20速度%20退化%20使用%20备用%20功率%20减少%20(SPR)%20电路
DOI：
10.1109/isscc.1995.535572
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发表时间：
1995
期刊：
影响因子：
--
通讯作者：
T. Sakurai
中科院分区：
文献类型：
--
作者：
K. Seta;H. Hara;T. Kuroda;M. Kakumu;T. Sakurai
多媒体LSI需要高速和低功耗，因为电池操作的便携性有时是多媒体设备的关键因素，同时提供每秒千兆操作（GOPS）的处理能力用于数字视频使用。为了了解电路延迟和功耗对电源电压（V/sub DD/）和MOSFET阈值电压（V/sub TH/）的依赖性，对一个典型的逻辑电路进行了研究。扇出被选择为5，其对应于ASIC中栅极负载的统计平均值。给出了一个模拟的延迟与V/sub DD/和V/sub TH/的关系。nMOS和pMOS选择相同的V/sub TH/。结果表明，如果V/sub TH/降低到0.3V，V/sub DD/可以降低到2V，同时保持速度在V/sub TH/= 0.7V和V/sub DD/= 3V，这是高速LSI的典型工作条件。在这种情况下，有源功耗降低了50%以上。
High-speed and low-power are required for multimedia LSIs, since portability with battery operation is sometimes the key factor for multimedia equipment, while delivering giga operations per second (GOPS) processing power for digital video use. To understand circuit delay and power dissipation dependence on power supply voltage (V/sub DD/) and threshold voltage of MOSFETs (V/sub TH/), a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. A simulated delay dependence on V/sub DD/ and V/sub TH/ is presented. The same V/sub TH/ is chosen for nMOS and pMOS. It is shown that if V/sub TH/ is reduced to 0.3V, V/sub DD/ can be decreased down to 2V while maintaining the speed at V/sub TH/=0.7V and V/sub DD/=3V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.