Fault-Tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support
Fault-Tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support
复制标题
具有硬件事务内存支持的 COTS 多核处理器上的容错执行
DOI:
10.1007/978-3-319-54999-6_2
复制
发表时间:
2017
影响因子:
1.8
通讯作者:
Youfeng Wu
中科院分区:
文献类型:
--
作者:
Florian Haas;Sebastian Weis;T. Ungerer;Gilles A. Pokam;Youfeng Wu
The demand for fault-tolerant execution on high performance computer systems increases due to higher fault rates resulting from smaller structure sizes. As an alternative to hardware-based lockstep solutions, software-based fault-tolerance mechanisms can increase the reliability of multi-core commercial-of-the-shelf (COTS) CPUs while being cheaper and more flexible. This paper proposes a software/hardware hybrid approach, which targets Intel’s current x86 multi-core platforms of the Core and Xeon family. We leverage hardware transactional memory (Intel TSX) to support implicit checkpoint creation and fast rollback. Redundant execution of processes and signature-based comparison of their computations provides error detection, and transactional wrapping enables error recovery. Existing applications are enhanced towards fault-tolerant redundant execution by post-link binary instrumentation. Hardware enhancements to further increase the applicability of the approach are proposed and evaluated with SPEC CPU 2006 benchmarks. The resulting performance overhead is 47% on average, assuming the existence of the proposed hardware support.
DOI:
10.1145/2901318.2901339
发表时间:
2016
期刊:
Proceedings of the Eleventh European Conference on Computer Systems
影响因子:
--
作者:
D. Kuvaiskii;R. Faqeh;P. Bhatotia;P. Felber;C. Fetzer
通讯作者:
C. Fetzer