TDC Architecture Study for the ATLAS Muon Tracker
TDC Architecture Study for the ATLAS Muon Tracker
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ATLAS Muon 跟踪器的 TDC 架构研究
DOI：
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发表时间：
1997
期刊：
影响因子：
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通讯作者：
Y. Arai
中科院分区：
文献类型：
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作者：
Y. Arai
已针对 ATLAS 精密 μ 子跟踪器研究了新型 TDC LSI 的架构。使用 Verilog 模拟器针对各种条件进行了密集模拟。最终芯片将采用 0.35 μm CMOS 技术制造。原型芯片的verilog RTL 级模型已经实现。还使用一代旧工艺 (0.5 μm) 进行了辐射硬度测试。
The architecture of a new TDC LSI has been studied for the ATLAS precision muon tracker. Intensive simulations have been performed using a Verilog simulator for various conditions. The final chip will be fabricated in a 0.35 μm CMOS technology. A verilog RTL level model for a prototype chip has been implemented. Radiation hardness tests using a one generation older process (0.5 μm) have also been done.