Design of VLSI implementation-oriented LDPC codes
Design of VLSI implementation-oriented LDPC codes
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DOI：
10.1109/vetecf.2003.1285102
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发表时间：
2003
期刊：
影响因子：
--
通讯作者：
Hao Zhong;Tong Zhang
中科院分区：
文献类型：
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作者：
Hao Zhong;Tong Zhang
近年来，低密度奇偶校验(LDPC)码因其优异的纠错性能和高度可并行化的译码方案而备受关注。然而，LDPC译码的有效VLSI实现仍然是一个巨大的挑战，也是决定我们如何在实际应用中很好地利用LDPC码的好处的关键问题。本文遵循码译码的联合设计思想，提出了一种构造LDPC码的半随机设计方案，该方案不仅具有很好的纠错性能，而且能有效地适用于部分并行的VLSI译码实现。相应的部分并行解码器具有非常规则的结构和简单的控制机制。计算机仿真表明，这种LDPC码具有与完全随机构造的LDPC码相当的很好的性能，但不太可能适用于部分并行的译码实现。
Recently, low-density parity-check (LDPC) codes have attracted much attention because of their excellent error-correcting performance and highly parallelizable decoding scheme. However, the effective VLSI implementation of an LDPC decoder remains a big challenge and is a crucial issue in determining how well we can exploit the benefits of the LDPC codes in real applications. In this paper, following the joint code and decoder design philosophy, we propose a semi-random design scheme to construct the LDPC codes that not only exhibit very good error-correcting performance but also effectively fit to partially parallel VLSI decoder implementations. The corresponding partially parallel decoder has a very regular structure and simple control mechanism. Our computer simulations show that such LDPC codes achieve very good performance comparable to their counterparts constructed in a fully random scheme, which however have little chance of fitting to partially parallel decoder implementations.