A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop
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DOI：
10.1109/jssc.2015.2473667
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发表时间：
2015-11-01
影响因子：
5.4
通讯作者：
Lacaita, Andrea L.
中科院分区：
文献类型：
--
作者：
Levantino, Salvatore;Marucci, Giovanni;Lacaita, Andrea L.
尽管乘法延迟锁定环允许以非常低的相位噪声和抖动进行时钟频率乘法，但它们的应用迄今为止仅限于整数N乘法，并且所实现的参考杂散性能通常受到时间偏移的限制。本文提出了第一个发表的乘法延迟锁定环，实现了精细的分数 N 频率分辨率，并引入了相位检测器偏移的自动消除。这两种功能都是通过在参考路径中插入数字时间转换器来实现的。所提出的合成器采用标准 65 nm CMOS 工艺实现，核心面积为 0.09 mm(2)，并通过 50 MHz 石英参考振荡器生成 1.6 至 1.9 GHz 的频率，分辨率为 190 Hz。在小数 N 模式下，集成 RMS 抖动（包括随机和确定性分量）在 3 mW 功耗下低于 1.4 ps，从而实现 -232 dB 的抖动功率品质因数。在整数 N 模式下，该电路在 2.4 mW 功率下实现了 0.47 ps 的 RMS 抖动，并且品质因数为 -243 dB。由于采用了自动偏移消除，参考杂散电平从 -32 dBc 降低至 -55 dBc。
Although multiplying delay-locked loops allow clock frequency multiplication with very low phase noise and jitter, their application has been so far limited to integer-N multiplication, and the achieved reference-spur performance has been typically limited by time offsets. This paper presents the first published multiplying delay-locked loop achieving fine fractional-N frequency resolution, and introduces an automatic cancellation of the phase detector offset. Both capabilities are enabled by insertion of a digital-to-time converter in the reference path. The proposed synthesizer, implemented in a standard 65 nm CMOS process, occupies a core area of 0.09 mm(2), and generates a frequency ranging between 1.6 and 1.9 GHz with a 190 Hz resolution from a 50 MHz quartz-based reference oscillator. In fractional-N mode, the integrated RMS jitter, including random and deterministic components, is below 1.4 ps at 3 mW power consumption, leading to a jitter-power figure of merit of -232 dB. In integer-N mode, the circuit achieves RMS jitter of 0.47 ps at 2.4 mW power and figure of merit of -243 dB. Thanks to the adoption of the automatic offset cancellation, the reference-spur level is reduced from -32 to -55 dBc.