Improvement of threshold voltage deviation in damascene metal gate transistors
Improvement of threshold voltage deviation in damascene metal gate transistors
复制标题
镶嵌金属栅晶体管阈值电压偏差的改善
DOI：
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发表时间：
2001
期刊：
影响因子：
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通讯作者：
T. Arikado
中科院分区：
文献类型：
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作者：
A. Yagishita;Tomohiro Saito;K. Nakajima;S. Inumiya;K. Matsuo;T. Shibata;Y. Tsunashima;K. Suguro;T. Arikado
金属栅功函数偏差（晶体取向偏差）被发现会导致半导体金属栅晶体管中的阈值电压偏差（/spl Delta/V/sub th/）。当通过使用无机CVD技术控制TiN功函数（晶体取向）时，表面沟道金属栅（Al/TiN或W/TiN）晶体管的/spl Δ/V/sub th/显著改善，并且发现其小于常规多晶硅栅晶体管的/spl Δ/V/sub th/。金属栅晶体管阈值电压偏差进一步减小的原因被认为是在金属栅工艺中使栅和栅氧化层上的热损伤和等离子体损伤最小化。为了证实CVD-TiN与高k栅介质的兼容性和无机CVD-TiN的技术优势，采用功函数控制的CVD-TiN金属栅和Ta/sub 2/O/sub 5/栅绝缘层，研制了亚100 nm高性能金属氧化物半导体场效应晶体管（MOSFET）。
The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, /spl Delta/V/sub th/ of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta/sub 2/O/sub 5/ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN.