DTC Linearization via Mismatch-Noise Cancellation for Digital Fractional- N PLLs
DTC Linearization via Mismatch-Noise Cancellation for Digital Fractional- N PLLs
复制标题
通过数字小数 N PLL 失配噪声消除实现 DTC 线性化
DOI：
10.1109/tcsi.2022.3200047
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发表时间：
2022
期刊：
影响因子：
--
通讯作者：
Galton, Ian
中科院分区：
文献类型：
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作者：
Helal, Eslam;Eissa, Amr I.;Galton, Ian
基于数字时间转换器（DTC）的量化噪声消除（QNC）最近被证明能够实现出色的分数PLL性能，但它需要高度线性的DTC。已知的DTC线性化策略包括涉及性能折衷的模拟域技术和相对于典型的所需PLL建立时间缓慢收敛的数字预失真技术。或者，实现为1位DTC级的级联的DTC可以在没有特殊技术的情况下被制成高度线性的，但是这样的DTC通常引入来自元件失配的过多误差，这迄今为止阻碍了它们在低抖动PLL中的使用。本文提出了一种背景校准技术，解决了这个问题，通过自适应地消除错误的DTC组件不匹配。该技术是完全数字化的，与一大类数字分数PLL兼容，并且具有比上述预失真技术低至少一个数量级的收敛时间。本文提出了一个严格的理论分析密切支持的仿真结果，量化的校准技术的收敛时间和噪声性能。
Digital-to-time converter (DTC) based quantization noise cancellation (QNC) has recently been shown to enable excellent fractional-PLL performance, but it requires a highly-linear DTC. Known DTC linearization strategies include analog-domain techniques which involve performance tradeoffs and digital predistortion techniques which converge slowly relative to typical required PLL settling times. Alternatively, a DTC implemented as a cascade of 1-bit DTC stages can be made highly linear without special techniques, but such DTCs typically introduce excessive error from component mismatches which has so far hindered their use in low-jitter PLLs. This paper presents a background calibration technique that addresses this issue by adaptively canceling error from DTC component mismatches. The technique is entirely digital, is compatible with a large class of digital fractional-PLLs, and has at least an order of magnitude lower convergence time than the above-mentioned predistortion techniques. The paper presents a rigorous theoretical analysis closely supported by simulation results which quantifies the calibration technique’s convergence time and noise performance.