Use of Statistical Timing Analysis on Real Designs
Use of Statistical Timing Analysis on Real Designs
复制标题
在实际设计中使用统计时序分析
DOI：
10.1109/date.2007.364531
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
J. Song
中科院分区：
文献类型：
--
作者：
A. Nardi;E. Tuncer;S. Naidu;A. Antonau;S. Gradinaru;Tao Lin;J. Song
关于统计静态时序分析（SSTA）、其动机、不同的实现方式及其运行时间/精度权衡，已经发表了大量文献。然而，非常有限的文献存在的适用性和使用模式，这种新技术的真实的设计。这项工作的重点是使用SSTA在真实的设计和它的实际好处和传统的设计流程的局限性。作者引入了两个新的指标来驱动优化：偏斜关键性和聚合敏感性。SSTA的实际好处是证明了时钟树分析，并正确建模的芯片上的变化。使用SSTA覆盖传统的角点分析和驱动优化也进行了讨论。结果报告的三个设计上实现了90纳米技术
A vast literature has been published on statistical static timing analysis (SSTA), its motivations, its different implementations and their runtime/accuracy trade-offs. However, very limited literature exists on the applicability and the usage models of this new technology on real designs. This work focuses on the use of SSTA in real designs and its practical benefits and limitations over the traditional design flow. The authors introduce two new metrics to drive the optimization: skew criticality and aggregate sensitivity. Practical benefits of SSTA are demonstrated for clock tree analysis, and correct modeling of on-chip-variations. The use of SSTA to cover the traditional corner analysis and to drive optimization is also discussed. Results are reported on three designs implemented on a 90nm technology