Designing fast asynchronous circuits
Designing fast asynchronous circuits
复制标题
设计快速异步电路
DOI：
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发表时间：
2001
期刊：
影响因子：
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通讯作者：
J. Lexau
中科院分区：
文献类型：
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作者：
I. Sutherland;J. Lexau
异步电路的五步设计过程有助于简化其逻辑并加快其操作。首先，假设控制器中的所有逻辑门都具有几乎一致的延迟。第二，使用均匀延迟假设来简化控制逻辑。第三，布置芯片以获得线长数据。第四，选择一个特定的延迟，并计算晶体管宽度，以将该特定延迟均匀地应用于控制中的所有逻辑门;本文展示了如何做到这一点。第五，用标准方法验证操作是否正确。特定的门延迟权衡了速度、面积和功耗;推迟选择它可以利用延迟来适应布局带来的限制。特定延迟的理论下限取决于设计中最复杂环路的逻辑工作量，并且值得注意的是，在给定足够宽的晶体管的情况下，与导线电容无关，但是导线电容对速度提出了实际界限。导线电阻的影响仍未得到研究。
A five-step design process for asynchronous circuits helps simplify their logic and speed their operation. First, assume that all logic gates in the control will have nearly uniform delay. Second, use the uniform delay assumption to simplify control logic. Third, lay out the chip to get wire length data. Fourth, choose a specific delay and calculate transistor widths to apply that specific delay uniformly to all logic gates in the control; this paper shows how. Fifth, verify correct operation with standard methods. The specific gate delay trades off speed, area, and power consumption; postponing its choice takes advantage of asynchrony to accommodate the limitations imposed by layout. The theoretical lower bound for specific delay depends on the logical effort of the most complex loop in the design and remarkably, is independent of wire capacitance, given wide enough transistors, but wire capacitance puts practical bounds on speed. The effect of wire resistance remains unexplored.