A 2.1-GHz PLL with −80dBc/−74dBc reference spur based on aperture-phase detector and phase-to-analog converter
A 2.1-GHz PLL with −80dBc/−74dBc reference spur based on aperture-phase detector and phase-to-analog converter
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DOI：
10.1109/asscc.2011.6123622
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发表时间：
2011-11
期刊：
影响因子：
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通讯作者：
Deyun Cai;Haipeng Fu;Junyan Ren;Wei Li;Ning Li;Hao Yu;K. Yeo
中科院分区：
文献类型：
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作者：
Deyun Cai;Haipeng Fu;Junyan Ren;Wei Li;Ning Li;Hao Yu;K. Yeo
本文提出了一种具有低功耗、低带内相位噪声和低参考杂散的2.1 GHz锁相环。一种新的孔径相位检测器（APD）在一个时间窗口内比较基准和VCO输出之间的相位，从而消除了分频器的功率和噪声贡献。在相位检测结束时，相位-模拟转换器（PAC）产生与相位误差成比例的模拟电压，然后控制随后的电荷泵（CP）电路的电流幅度。当传输到PLL输出时，与传统PLL相比，CP噪声不会乘以N2，这导致PLL具有较低的带内相位噪声。在该电路中，当锁相环锁定时，充放电电流具有等脉宽和等幅值，接近于零，从而实现了低参考杂散和超低功耗。该锁相环采用TSMC0.13 μ mCMOS工艺实现，在1.2V电源电压下功耗为2.5mA，不包括PAD的核心面积为0.48mm × 0.86mm。测量结果表明，PLL的基准杂散电平为− 80 dBc/− 74 dBc，带内相位噪声为−103 dBc/Hz（100 kHz失调）。
This paper presents a 2.1-GHz PLL with low power consumption, low in-band phase noise and low reference spur. A new aperture-phase detector (APD) compares the phases between reference and VCO output in a time window, which eliminates the power and noise contributions from the divider. At the end of phase detection, a phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error and then controls the current amplitude of the following charge pump (CP) circuit. When transferred to PLL output, CP noise is not multiplied by N2 compared with a conventional PLL, which leads to the PLL with lower in-band phase noise. In the proposed CP, the charging and discharging currents have equal pulse width and equal amplitude close to zero when PLL is locked, resulting in a low reference spur and super-low power consumption of CP. The proposed PLL is implemented in TSMC 0.13μm CMOS process, which consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm × 0.86 mm excluding PAD. Measurement results indicate that the PLL achieves a reference spur level of −80dBc/−74dBc, and an in-band phase noise of −103 dBc/Hz at 100 kHz offset.